ports in generated vhdl in wrong order

[Tuukka Toivonen]

My problem is shown in the following piece of VHDL:

-- VHDL automatically generated from facet test{sch}
entity test is port(in1_0_, in1_1_, in1_2_, in1_3_, in2_0_, in2_1_,
 in2_2_, in2_3_, crin: in BIT; out_0_, out_1_, out_2_, out_3_, crout:
 out BIT);
  end test;
architecture test_BODY of test is
  component ADD4_CLA port(A_0_, A_1_, A_2_, A_3_, B_0_, B_1_, B_2_,
 B_3_, Cin: in BIT; S_0_, S_1_, S_2_, S_3_, Cout: out BIT);
    end component;
begin
  node6: ADD4_CLA port map(in2_0_, in2_1_, in2_2_, in2_3_, crin,
 in1_0_, in1_1_, in1_2_, in1_3_, out_0_, out_1_, out_2_, out_3_,
 crout);
end test_BODY;

Here exports should be mapped as
A[0:3] -> in2[0:3] (input)
B[0:3] -> in1[0:3] (input)
S[0:3] -> out[0:3] (output)
Cin -> crin (input)
Cout -> crout (output)

The VHDL is generated from a schematics view, which contains an icon for
ADD4_CLA.

By comparing the lines "component ADD4_CLA..." and "node6: ADD4_CLA..."
you can see that ports in the latter line are in wrong order.
Here are results of my investigations:

The ports for the first line are printed in the function
"vhdl_addportlist". This function decides whether a port is input or
output by checking 
        schematics prototype cnp->firstportproto->userbits
which seems to be certainly correct.

The ports for the latter line are printed in the function 
"vhdl_addrealports". This function decides whether a port is input or 
output by checking 
        icon prototype np->firstportproto->userbits
which correlates with the fact that
        icon instance ni->firstportarcinst->proto
points also in np->firstportproto

However, cnp->firstportproto->userbits differs 
from np->firstportproto->userbits (where the latter is actually wrong) and
this is why the ports get in wrong order: their order depends whether they
are specified as input or output ports, but this specification is
inconsistent whether we look at the icon or schematics prototype.

http://www.ee.oulu.fi/~tuukkat/electric/bug.ps
contains a snapshot picture of the datastructures (taken with DDD) which
hopefully show what's going on.

Note: standard electric wouldn't support busses here at all, I was using
my own version which has bus-support patched in. However, I don't think my
patch makes any difference, probably this same problem could occur in the
standard electric too.

I deleted the icon (and the schematics, where it was embedded in) and
recreated it. After this it seems to work, but it took awfully long to
find out what was wrong in the first case.

My question is: why do electric use inconsistently ports from icon
and schematic view? Is there a deep reason to do so, or could it be fixed?

Another strange thing is, why the ports were inconsistent in the first
place? Maybe there is a bug hidden elsewhere?

The following patch would fix my problem and make electric--as I see it--a
bit more consistent (although I don't really need it now since I realized
it was enough just to recreate the icon for ADD4_CLA).

--- vhdl.c.orig3        Tue Jul 10 17:23:36 2001
+++ vhdl.c      Wed Jul 11 16:54:07 2001
@@ -1434,28 +1434,28 @@
                        if (pass == 0)
                        {
                                /* must be an input port */
-                               if ((pp->userbits&STATEBITS) != INPORT) 
continue;
+                               if ((cpp->userbits&STATEBITS) != INPORT) 
continue;
                        }
                        if (pass == 1)
                        {
                                /* must be an output port */
-                               if ((pp->userbits&STATEBITS) != OUTPORT) 
continue;
+                               if ((cpp->userbits&STATEBITS) != OUTPORT) 
continue;
                        }
                        if (pass == 2)
                        {
                                /* must be an output port */
-                               if ((pp->userbits&STATEBITS) != PWRPORT) 
continue;
+                               if ((cpp->userbits&STATEBITS) != PWRPORT) 
continue;
                        }
                        if (pass == 3)
                        {
                                /* must be an output port */
-                               if ((pp->userbits&STATEBITS) != GNDPORT) 
continue;
+                               if ((cpp->userbits&STATEBITS) != GNDPORT) 
continue;
                        }
                        if (pass == 4)
                        {
                                /* any other port type */
-                               if ((pp->userbits&STATEBITS) == INPORT || 
(pp->userbits&STATEBITS) == OUTPORT ||
-                                       (pp->userbits&STATEBITS) == PWRPORT || 
(pp->userbits&STATEBITS) == GNDPORT)
+                               if ((cpp->userbits&STATEBITS) == INPORT || 
(cpp->userbits&STATEBITS) == OUTPORT ||
+                                       (cpp->userbits&STATEBITS) == PWRPORT || 
(cpp->userbits&STATEBITS) == GNDPORT)
                                                continue;
                        }
 
@@ -1498,7 +1498,7 @@
                        }
 
                        /* if multiple connections, get them all */
-                       if ((pp->userbits&PORTISOLATED) != 0)
+                       if ((cpp->userbits&PORTISOLATED) != 0)
                        {
                                for(pi = ni->firstportarcinst; pi != 
NOPORTARCINST; pi = pi->nextportarcinst)
                                {