****library: "noname"
version: 6.04
aids: 14
aidname: user
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aidname: compaction
aidname: pla
aidname: routing
aidname: silicon-compiler
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SC_nwell_size[01,00/00]: 20400
aidname: vhdl-compiler
aidname: compensation
aidname: logeffort
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LE_state[01,00/00]: 3
aidname: network
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[01,00/00]: 1
D[01,00/00]: 1
<[01,00/00]: 1
NET_use_port_names[01,00/00]: 0
NET_compare_hierarchy[01,00/00]: 1
aidname: drc
aidname: erc
aidname: simulation
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SIM_fasthenry_defthickness[01,00/00]: 800
aidname: project
userbits: 70
techcount: 16
techname: generic lambda: 2000
techname: nmos lambda: 4000
techname: cmos lambda: 4000
techname: mocmos lambda: 400
variables: 1
TECH_last_state[01,00/00]: 8
techname: mocmosold lambda: 2000
techname: mocmossub lambda: 400
variables: 1
TECH_last_state[01,00/00]: 8
techname: bicmos lambda: 2000
techname: rcmos lambda: 2000
techname: cmosdodn lambda: 2000
techname: bipolar lambda: 4000
techname: schematic lambda: 4000
techname: fpga lambda: 2000
techname: pcb lambda: 2540000
techname: artwork lambda: 4000
variables: 1
TECH_last_state[01,00/00]: 0
techname: gem lambda: 2000
techname: efido lambda: 20000
view: schematic-page-2{p2}
view: schematic-page-1{p1}
view: layout{lay}
view: schematic{sch}
view: icon{ic}
view: documentation{doc}
view: compensated{comp}
view: skeleton{sk}
view: Verilog{ver}
view: VHDL{vhdl}
view: netlist{net}
view: netlist-als-format{net-als}
view: netlist-quisc-format{net-quisc}
view: netlist-silos-format{net-silos}
view: netlist-rsim-format{net-rsim}
view: netlist-netlisp-format{net-netlisp}
view: simulation-snapshot{sim}
view: unknown{}
cellcount: 9
maincell: 2
***cell: 0
name: my_mux2{ic}
version: 1
creationdate: 998063300
revisiondate: 998063407
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aadirty: 6638
userbits: 131074
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userbits: 3072
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*port: wire
arc: 3
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type: schematic:Mux
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celldone: my_mux2
***cell: 1
name: my_mux2{sch}
version: 1
creationdate: 998062001
revisiondate: 998063560
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aadirty: 6638
userbits: 393216
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SIM_window_signal_order[011204,00/0400]: ["NET3","NET2","NET1","O","B","S","A","NET4","PINV1"]
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NODE_name[04,00/0400]: "node13"
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type: schematic:Off-Page
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NODE_name[04,00/0400]: "node9"
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arc: 6
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NODE_name[04,00/0400]: "node10"
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NODE_name[04,00/0400]: "node11"
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NODE_name[04,00/0400]: "node12"
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NODE_name[04,00/0400]: "node8"
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arc: 5
arc: 12
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NODE_name[04,00/0400]: "node7"
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arc: 3
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NODE_name[04,00/0400]: "node6"
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arc: 8
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arc: 8
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NODE_name[04,00/0400]: "node4"
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arc: 14
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ARC_name[04,00/0400]: "net4"
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ARC_name[04,00/0400]: "net3"
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ARC_name[04,00/0400]: "net2"
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nodeport: y
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nodeport: a
xpos: -112000 ypos: 16000
variables: 1
ARC_name[04,00/0400]: "net1"
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type: schematic:wire
width: 0 length: 60000
userbits: 813700738
*end: 0
node: 7
nodeport: a
xpos: -112000 ypos: 44000
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nodeport: wire
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type: schematic:wire
width: 0 length: 16000
userbits: 813700738
*end: 0
node: 13
nodeport: a
xpos: -156000 ypos: 16000
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type: schematic:wire
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nodeport: wire
xpos: -172000 ypos: 44000
*end: 1
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nodeport: wire
xpos: -172000 ypos: 16000
celldone: my_mux2
***cell: 2
name: mux2test{sch}
version: 1
creationdate: 998061873
revisiondate: 998063487
lowx: -72000 highx: 32000 lowy: -40000 highy: 24000
aadirty: 6638
userbits: 262144
nodes: 6 arcs: 5 porttypes: 4
variables: 1
SIM_window_signal_order[04204,00/0400]: ["OUTNV","SELECT","IN_B","IN_A"]
**node: 0
type: schematic:Wire_Pin
lowx: -22000 highx: -18000 lowy: -38000 highy: -34000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 2
arc: 3
**node: 1
type: schematic:Off-Page
lowx: 16000 highx: 32000 lowy: 0 highy: 8000
rotation: 0 transpose: 0
userbits: 68608
variables: 1
NODE_name[04,00/0400]: "node1"
*port: a
arc: 4
*port: y
exported: 3
**node: 2
type: schematic:Off-Page
lowx: -60000 highx: -44000 lowy: -40000 highy: -32000
rotation: 0 transpose: 0
userbits: 3072
variables: 1
NODE_name[04,00/0400]: "node2"
*port: y
arc: 3
exported: 2
**node: 3
type: schematic:Off-Page
lowx: -72000 highx: -56000 lowy: -8000 highy: 0
rotation: 0 transpose: 0
userbits: 3072
variables: 1
NODE_name[04,00/0400]: "node3"
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arc: 0
exported: 1
**node: 4
type: schematic:Off-Page
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rotation: 0 transpose: 0
userbits: 3072
variables: 1
NODE_name[04,00/0400]: "node4"
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arc: 1
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type: [0]
lowx: -36000 highx: -4000 lowy: -20000 highy: 24000
rotation: 0 transpose: 0
descript: 9/1024
userbits: 67588
variables: 1
NODE_name[04,00/0400]: "node5"
*port: a
arc: 1
*port: b
arc: 0
*port: o
arc: 4
*port: s
arc: 2
**porttype: 0
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subport: y
name: in_a
descript: 2195456/512
userbits: -2147460608
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subnode: 3
subport: y
name: in_b
descript: 2195456/512
userbits: -2147460608
**porttype: 2
subnode: 2
subport: y
name: select
descript: 2211840/512
userbits: -2147460608
**porttype: 3
subnode: 1
subport: y
name: out
descript: 32768/512
userbits: -1879025152
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nodeport: y
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nodeport: a
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width: 0 length: 16000
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node: 0
nodeport: wire
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*end: 1
node: 5
nodeport: s
xpos: -20000 ypos: -20000
**arc: 3
type: schematic:wire
width: 0 length: 24000
userbits: 813694978
*end: 0
node: 2
nodeport: y
xpos: -44000 ypos: -36000
*end: 1
node: 0
nodeport: wire
xpos: -20000 ypos: -36000
**arc: 4
type: schematic:wire
width: 0 length: 20000
userbits: 813700742
*end: 0
node: 1
nodeport: a
xpos: 16000 ypos: 4000
*end: 1
node: 5
nodeport: o
xpos: -4000 ypos: 4000
celldone: mux2test
***cell: 3
name: mux2test{vhdl}
version: 1
creationdate: 998063210
revisiondate: 998063210
lowx: 0 highx: 0 lowy: 0 highy: 0
aadirty: 2542
userbits: 262144
nodes: 0 arcs: 0 porttypes: 0
variables: 1
FACET_message[012204,00/0400]: ["-- VHDL automatically generated from facet mux2test{sch}","entity mux2test is port(i, j, o, xx: inout BIT);","  end mux2test;","architecture mux2test_BODY of mux2test is","  component mux2 port(a1, a2, s: in BIT; y: out BIT);","    end component;","begin","  node5: mux2 port map(i, j, xx, o);","end mux2test_BODY;",""]
celldone: mux2test
***cell: 4
name: mux2test{net-als}
version: 1
creationdate: 998063210
revisiondate: 998063210
lowx: 0 highx: 0 lowy: 0 highy: 0
aadirty: 2542
userbits: 262144
nodes: 0 arcs: 0 porttypes: 0
variables: 1
FACET_message[012204,00/0400]: ["#*************************************************","#  ALS Netlist file","#","#  File Creation:    Fri Aug 17 18:46:50 2001","#-------------------------------------------------","","model mux2test(i, j, o, xx)","node5: mux2(i, j, xx, o)","","#********* End of netlist *******************"]
celldone: mux2test
***cell: 5
name: my_mux2{vhdl}
version: 1
creationdate: 998063221
revisiondate: 998063221
lowx: 0 highx: 0 lowy: 0 highy: 0
aadirty: 2542
userbits: 262144
nodes: 0 arcs: 0 porttypes: 0
variables: 1
FACET_message[024204,00/0400]: ["-- VHDL automatically generated from facet mux2{sch}","entity mux2 is port(a, b, s: in BIT; o: out BIT);","  end mux2;","architecture mux2_BODY of mux2 is","  component and2 port(a1, a2: in BIT; y: out BIT);","    end component;","  component inverter port(a: in BIT; y: out BIT);","    end component;","  component nand2 port(a1, a2: in BIT; y: out BIT);","    end component;","  signal net4, net2, net3, net1: BIT;","  signal PINV1: BIT;","begin","  node8: nand2 port map(a, b, net3);","  node7: nand2 port map(s, net1, net2);","  node6: and2 port map(net2, net3, net4);","  node4: inverter port map(b, net1);","  PSEUDO_INVERT1: inverter port map(net4, PINV1);","end mux2_BODY;",""]
celldone: my_mux2
***cell: 6
name: my_mux2{net-als}
version: 1
creationdate: 998063221
revisiondate: 998063221
lowx: 0 highx: 0 lowy: 0 highy: 0
aadirty: 2542
userbits: 262144
nodes: 0 arcs: 0 porttypes: 0
variables: 1
FACET_message[072204,00/0400]: ["#*************************************************","#  ALS Netlist file","#","#  File Creation:    Fri Aug 17 18:47:01 2001","#-------------------------------------------------","","model mux2(a, b, s, o)","node8: nand2(a, b, net3)","node7: nand2(s, net1, net2)","node6: and2(net2, net3, net4)","node4: inverter(b, net1)","PSEUDO_INVERT1: inverter(net4, PINV1)","","#********* End of netlist *******************","","# Built-in model for inverter","gate inverter(a,z)","t: delta=1.33e-9","i: a=L o: z=H","t: delta=1.07e-9","i: a=H o: z=L","t: delta=0","i: a=X o: z=X","load: a=1.0","","# Built-in model for and2","model and2(a1,a2,z)","g1: and2fun(a1,a2,out)","g2: and2buf(out,z)","gate and2fun(a1,a2,z)","t: delta=1.33e-9","i: a1=L o: z=H","i: a2=L o: z=H","t: delta=1.07e-9","i: a1=H a2=H o: z=L","t: delta=0","i: o: z=X","load: a1=1.0 a2=1.0","gate and2buf(in,out)","t: delta=0.56e-9","i: in=H    o: out=L","t: delta=0.41e-9","i: in=L    o: out=H","t: delta=0","i: in=X    o: out=X","","# Built-in model for nand2","model nand2(a1,a2,z)","g1: nand2fun(a1,a2,z)","gate nand2fun(a1,a2,z)","t: delta=1.33e-9","i: a1=L o: z=H","i: a2=L o: z=H","t: delta=1.07e-9","i: a1=H a2=H o: z=L","t: delta=0","i: o: z=X","load: a1=1.0 a2=1.0"]
celldone: my_mux2
***cell: 7
name: mux2test{vhdl}
version: 2
creationdate: 998063493
revisiondate: 998063493
lowx: 0 highx: 0 lowy: 0 highy: 0
aadirty: 6638
userbits: 0
nodes: 0 arcs: 0 porttypes: 0
variables: 1
FACET_message[036204,00/0400]: ["-- VHDL automatically generated from facet mux2test{sch}","entity mux2test is port(in_a, in_b, select: in BIT; outNV: out BIT);","  end mux2test;","architecture mux2test_BODY of mux2test is","  component my_mux2 port(a, s, b: in BIT; o: out BIT);","    end component;","begin","  node5: my_mux2 port map(in_a, select, in_b, outNV);","end mux2test_BODY;","","-- VHDL automatically generated from facet my_mux2{sch}","entity my_mux2 is port(a, s, b: in BIT; o: out BIT);","  end my_mux2;","architecture my_mux2_BODY of my_mux2 is","  component and2 port(a1, a2: in BIT; y: out BIT);","    end component;","  component inverter port(a: in BIT; y: out BIT);","    end component;","  component nand2 port(a1, a2: in BIT; y: out BIT);","    end component;","  signal net1, net3, net2: BIT;","  signal PINV1: BIT;","begin","  node8: nand2 port map(a, s, net3);","  node7: nand2 port map(b, net1, net2);","  node6: and2 port map(net2, net3, o);","  node4: inverter port map(s, net1);","  PSEUDO_INVERT1: inverter port map(o, PINV1);","end my_mux2_BODY;",""]
celldone: mux2test
***cell: 8
name: mux2test{net-als}
version: 2
creationdate: 998063493
revisiondate: 998063493
lowx: 0 highx: 0 lowy: 0 highy: 0
aadirty: 6638
userbits: 0
nodes: 0 arcs: 0 porttypes: 0
variables: 1
FACET_message[075204,00/0400]: ["#*************************************************","#  ALS Netlist file","#","#  File Creation:    Fri Aug 17 18:51:33 2001","#-------------------------------------------------","","model my_mux2(a, s, b, o)","node8: nand2(a, s, net3)","node7: nand2(b, net1, net2)","node6: and2(net2, net3, o)","node4: inverter(s, net1)","PSEUDO_INVERT1: inverter(o, PINV1)","","model mux2test(in_a, in_b, select, outNV)","node5: my_mux2(in_a, select, in_b, outNV)","","#********* End of netlist *******************","","# Built-in model for inverter","gate inverter(a,z)","t: delta=1.33e-9","i: a=L o: z=H","t: delta=1.07e-9","i: a=H o: z=L","t: delta=0","i: a=X o: z=X","load: a=1.0","","# Built-in model for and2","model and2(a1,a2,z)","g1: and2fun(a1,a2,out)","g2: and2buf(out,z)","gate and2fun(a1,a2,z)","t: delta=1.33e-9","i: a1=L o: z=H","i: a2=L o: z=H","t: delta=1.07e-9","i: a1=H a2=H o: z=L","t: delta=0","i: o: z=X","load: a1=1.0 a2=1.0","gate and2buf(in,out)","t: delta=0.56e-9","i: in=H    o: out=L","t: delta=0.41e-9","i: in=L    o: out=H","t: delta=0","i: in=X    o: out=X","","# Built-in model for nand2","model nand2(a1,a2,z)","g1: nand2fun(a1,a2,z)","gate nand2fun(a1,a2,z)","t: delta=1.33e-9","i: a1=L o: z=H","i: a2=L o: z=H","t: delta=1.07e-9","i: a1=H a2=H o: z=L","t: delta=0","i: o: z=X","load: a1=1.0 a2=1.0"]
celldone: mux2test