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Re: [Discuss-gnuradio] CORDIC in USRP TX path
From: |
Christian Meier |
Subject: |
Re: [Discuss-gnuradio] CORDIC in USRP TX path |
Date: |
Thu, 08 Oct 2009 16:42:32 +0100 |
User-agent: |
Thunderbird 2.0.0.23 (Windows/20090812) |
Hi once more,
I am currently writing a patch that reactivates the disabled and out of
date integration of the tx cordic inside FPGA.
If this works and fits into the FPGA, I plan to use it for getting more
tx and rx channels over the same daugtherboard with different baseband
offsets.
For this to work the tx and rx pipelines of a 2rx + 2tx configuration
have to be combined after tx_chain / before rx_chain.
This is done in a tx_combiner module.
Find attached the current progress as a patch.
I haven't neither tested nor synthesized it yet at all. I just wanted to
give a base for discussion.
If someone has any comments or further ideas on that, please let me know.
By the way, what is the firmware/fpga_regs0.h file good for? I didn't
find any file that uses these defines, or any .v file that includes
fpga_regs0.v.
For the patch to compile we also need some new register definitions of
FR_TX_(FREQ|PHASE)_[01] and FR_TX_COMBINER.
What do you think of this idea?
Thanks
Christian
Christian Meier wrote:
Hi,
I noticed that there is a hardcoded "`define NOCORDIC_TX" inside
tx_chain.v
Does anyone know why this is disabled?
Is it a problem of FPGA size or are there any bugs inside tx_chain
with NOCORDIC_TX not defined?
Christian
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Index: sdr_lib/tx_chain.v
===================================================================
--- sdr_lib/tx_chain.v (revision 11642)
+++ sdr_lib/tx_chain.v (working copy)
@@ -26,13 +26,16 @@
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
- input wire [31:0] freq,
+ input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
+ parameter FREQADDR = 0;
+ parameter PHASEADDR = 0;
+
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i
@@ -45,19 +48,20 @@
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );
-`define NOCORDIC_TX
+//`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
- phase_acc phase_acc_tx
+ phase_acc #(FREQADDR,PHASEADDR,32) tx_phase_acc
(.clk(clock),.reset(reset),.enable(enable),
- .strobe(sample_strobe),.freq(freq),.phase(phase) );
-
- cordic tx_cordic_0
- ( .clock(clock),.reset(reset),.enable(sample_strobe),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .strobe(sample_strobe),.phase(phase) );
+
+ cordic tx_cordic
+ ( .clock(clock),.reset(reset),.enable(enable),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
Index: sdr_lib/tx_combiner.v
===================================================================
--- sdr_lib/tx_combiner.v (revision 0)
+++ sdr_lib/tx_combiner.v (revision 0)
@@ -0,0 +1,31 @@
+`include "../../firmware/include/fpga_regs_common.v"
+`include "../../firmware/include/fpga_regs_standard.v"
+
+module tx_combiner
+ (input clock, input reset, input enable,
+ input wire [6:0] serial_addr, input wire [31:0] serial_data, input
serial_strobe,
+ input wire [15:0] i_in_0, output reg [15:0] q_in_0,
+ input wire [15:0] i_in_1, output reg [15:0] q_in_1,
+ output wire [15:0] i_out_0, output reg [15:0] q_out_0,
+ outout wire [15:0] i_out_1, output reg [15:0] q_out_1);
+
+ wire [31:0] tx_control;
+ reg [15:0] i_sum, wire [15:0] q_sum;
+
+ setting_reg #(`FR_TX_COMBINER)
sr_tx_combiner(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),
+
.in(serial_data),.out(tx_control));
+
+ always @(posedge clock)
+ begin
+ i_sum <= #1 i_in_1 + i_in_0;
+ q_sum <= #1 q_in_1 + q_in_0;
+ end
+
+
+ assign i_out_0 = tx_control[1] ? (tx_control[0] ? i_in_1 : i_sum) :
(tx_control[0] ? 16'b0 : i_in_0);
+ assign q_out_0 = tx_control[1] ? (tx_control[0] ? q_in_1 : q_sum) :
(tx_control[0] ? 16'b0 : q_in_0);
+ assign i_out_1 = tx_control[3] ? (tx_control[2] ? 16'b0 : i_in_0) :
(tx_control[2] ? i_in_1 : i_sum);
+ assign q_out_1 = tx_control[3] ? (tx_control[2] ? 16'b0 : q_in_0) :
(tx_control[2] ? q_in_1 : q_sum);
+
+endmodule // adc_interface
+
Index: toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
--- toplevel/usrp_inband_usb/usrp_inband_usb.v (revision 11642)
+++ toplevel/usrp_inband_usb/usrp_inband_usb.v (working copy)
@@ -102,6 +102,11 @@
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
+
+ // TX combining
+ wire [15:0] i_forw_0, i_forw_1, q_forw_0, q_forw_1;
+ wire [15:0] i_comb_0, i_comb_1, q_forw_0, q_comb_1;
+
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; //
bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
@@ -187,31 +192,46 @@
`endif
`ifdef TX_EN_0
- tx_chain tx_chain_0
+ tx_chain #(`FR_TX_FREQ_0,`FR_TX_PHASE_0) tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
- .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_forw_0),.q_out(q_forw_0) );
`else
- assign i_out_0=16'd0;
- assign q_out_0=16'd0;
+ assign i_forw_0=16'd0;
+ assign q_forw_0=16'd0;
`endif
`ifdef TX_EN_1
- tx_chain tx_chain_1
+ tx_chain #(`FR_TX_FREQ_1,`FR_TX_PHASE_1) tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
- .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_forw_1),.q_out(q_forw_1) );
`else
- assign i_out_1=16'd0;
- assign q_out_1=16'd0;
+ assign i_forw_1=16'd0;
+ assign q_forw_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
-
+
+'ifdef TX_COMBINING
+ tx_combiner tx_chain_combiner
+ ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
+
.seral_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .i_in_0(i_forw_0), .q_in_0(q_forw_0), .i_in_1(i_forw_1),
.q_in_1(q_forw_1),
+ .i_out_0(i_out_0), .q_out_0(q_out_0), .i_out_1(i_out_1),
.q_out2_1(q_out_1));
+'else
+ assign i_out_0=i_forw_0;
+ assign q_out_0=q_forw_0;
+ assign i_out_1=i_forw_1;
+ assign q_out_1=q_forw_1;
+'endif
+
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 :
i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 :
i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 :
i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;