Re: CCSDS BER PLOT

[U L]

One thing I think might be an issue is that you have no delay between your source reference and your BER block. Usually the FEC decoders (and possibly the encoder?) may output blocks of 0s before they output the samples that correspond to your inputs. I don't know much about those FEC blocks specifically, but maybe the docs have some info on their delays. You can just insert a delay block b/w your random source and the ber block to align the input and output bits.

Hope that helps,

Jared.

On Sat, Aug 12, 2023 at 4:28 AM Jiya Johnson <jiyajohnson10@gmail.com> wrote:

Dear community

   Need help for BER plot using the above flowgraph its always coming 10^-1.17 and whenever I tried to change the noise voltage the values are not changing.

Please find the attached GRC file for your reference.

Regards, JIYA JOHNSON