[Gnucap-devel] logic (Re: gnucap sandbox)

[Felix Salfelder]

On Mon, Apr 22, 2019 at 08:45:05PM +0200, Patrick Mulder wrote:
> 2) on the gnucap python i saw a statement "set lang verilog" - where would
> i start to so some basic verilog commands (wire, register, simple gates on
> event) ?

the "set lang verilog" command hands over the input parsing to the
verilog language plugin. as you might have found, the shipped version of
this plugin essentially implements netlisting (some paramset and device
instanciation), and running commands (not part of standard verilog). the
wire, and register commands as well as the events in verilog are used
in, or to describe, component models.

generating component models is more involved. a possible approach is
to turn a model description into a plugin written in a programming
language. another approach is to interpret the model or use some
intermediate bytecode whatosoever. there is a tradeoff between speed and
other things such as (maybe) flexibility.

we have a model compiler "modelgen" that reads models, in a language
that predates verilog. it writes plugins written in C++ and it is
limited to analog component models.  E.g. the built-in semiconductor
models are partly implemented in modelgen langage. The intent and plan
is to also support a sensible subset of verilog-a in a modelgen style
compiler. and then possibly include the digital/mixed modelling
features you mention. it is not there yet [1].

somewhat independently, i have started the logic device rewrite with the
aim to support verilog-ams "connectmodule" semantics. this will provide
custom mixed signal behavioural models -- limited to C++ (probably also
Python) implementations at the moment ([2], there is something on the
mailing list about it). it's all plugins. perhaps they should be
standalone and/or part of gnucap-python...

cheers
felix

[1] https://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git/
[2] https://git.savannah.gnu.org/cgit/gnucap.git/log/?h=conn-5