Re: [Help-smalltalk] [PATCH 1/4] embedded: Use more registers on ARM as there are plenty and reduce the alignment

[Paolo Bonzini]

Il 05/05/2013 11:25, Holger Hans Peter Freyther ha scritto:
> 2013-04-25  Holger Hans Peter Freyther  <address@hidden>
> 
>       * libgst/md-config.h: Add cases for the ARM architecture.

Ok.

Paolo

> ---
>  libgst/ChangeLog   |    4 ++++
>  libgst/md-config.h |   10 ++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/libgst/ChangeLog b/libgst/ChangeLog
> index 9cf1626..4abaa9a 100644
> --- a/libgst/ChangeLog
> +++ b/libgst/ChangeLog
> @@ -1,3 +1,7 @@
> +2013-04-25  Holger Hans Peter Freyther  <address@hidden>
> +
> +     * libgst/md-config.h: Add cases for the ARM architecture.
> +
>  2013-04-28  Holger Hans Peter Freyther  <address@hidden>
>  
>       * libgst/cint.c: Bind link, fsync, sync for additional C level access.
> diff --git a/libgst/md-config.h b/libgst/md-config.h
> index 260cac0..862fdfd 100644
> --- a/libgst/md-config.h
> +++ b/libgst/md-config.h
> @@ -66,6 +66,16 @@
>  # define __DECL_REG3 __asm("%l2")
>  #endif
>  
> +#if defined(__arm__)
> +/* We have plenty of registers on ARM but do not enable pipeline */
> +# define REG_AVAILABILITY 2
> +# define __DECL_REG1 __asm("r4")
> +# define __DECL_REG2 __asm("r5")
> +# define __DECL_REG3 __asm("r6")
> +# define BRANCH_REGISTER(name) register void *name __asm("r7")
> +# define L1_CACHE_SHIFT 4
> +#endif
> +
>  #if !defined(__DECL_REG1) && defined(__alpha__)
>  # define REG_AVAILABILITY 2
>  /* Note: REG3 causes compile problems when trying to fit 64-bit stuff in
>