[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 15/24] target/arm: Extract HA and HD in aa64_va_parameters
From: |
Richard Henderson |
Subject: |
[PATCH v4 15/24] target/arm: Extract HA and HD in aa64_va_parameters |
Date: |
Mon, 10 Oct 2022 20:19:02 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 2 ++
target/arm/helper.c | 8 +++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c3c3920ded..76ec7ee8cc 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1041,6 +1041,8 @@ typedef struct ARMVAParameters {
bool hpd : 1;
bool tsz_oob : 1; /* tsz has been clamped to legal range */
bool ds : 1;
+ bool ha : 1;
+ bool hd : 1;
ARMGranuleSize gran : 2;
} ARMVAParameters;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c672903f43..4487957e5d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10470,7 +10470,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
ARMMMUIdx mmu_idx, bool data)
{
uint64_t tcr = regime_tcr(env, mmu_idx);
- bool epd, hpd, tsz_oob, ds;
+ bool epd, hpd, tsz_oob, ds, ha, hd;
int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
ARMGranuleSize gran;
ARMCPU *cpu = env_archcpu(env);
@@ -10489,6 +10489,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
epd = false;
sh = extract32(tcr, 12, 2);
ps = extract32(tcr, 16, 3);
+ ha = extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu);
+ hd = extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu);
ds = extract64(tcr, 32, 1);
} else {
/*
@@ -10510,6 +10512,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
hpd = extract64(tcr, 42, 1);
}
ps = extract64(tcr, 32, 3);
+ ha = extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu);
+ hd = extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu);
ds = extract64(tcr, 59, 1);
}
@@ -10581,6 +10585,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
.hpd = hpd,
.tsz_oob = tsz_oob,
.ds = ds,
+ .ha = ha,
+ .hd = ha && hd,
.gran = gran,
};
}
--
2.34.1
- Re: [PATCH v4 06/24] target/arm: Restrict tlb flush from vttbr_write to vmid change, (continued)
- [PATCH v4 04/24] target/arm: Add ARMMMUIdx_Phys_{S,NS}, Richard Henderson, 2022/10/10
- [PATCH v4 07/24] target/arm: Split out S1Translate type, Richard Henderson, 2022/10/10
- [PATCH v4 11/24] target/arm: Split out get_phys_addr_twostage, Richard Henderson, 2022/10/10
- [PATCH v4 13/24] target/arm: Add ptw_idx to S1Translate, Richard Henderson, 2022/10/10
- [PATCH v4 12/24] target/arm: Use bool consistently for get_phys_addr subroutines, Richard Henderson, 2022/10/10
- [PATCH v4 14/24] target/arm: Add isar predicates for FEAT_HAFDBS, Richard Henderson, 2022/10/10
- [PATCH v4 15/24] target/arm: Extract HA and HD in aa64_va_parameters,
Richard Henderson <=
- [PATCH v4 09/24] target/arm: Move be test for regime into S1TranslateResult, Richard Henderson, 2022/10/10
- [PATCH v4 19/24] target/arm: Fix fault reporting in get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 16/24] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Richard Henderson, 2022/10/10
- [PATCH v4 17/24] target/arm: Add ARMFault_UnsuppAtomicUpdate, Richard Henderson, 2022/10/10
- [PATCH v4 18/24] target/arm: Remove loop from get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 10/24] target/arm: Use softmmu tlbs for page table walking, Richard Henderson, 2022/10/10
- [PATCH v4 21/24] target/arm: Consider GP an attribute in get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 20/24] target/arm: Don't shift attrs in get_phys_addr_lpae, Richard Henderson, 2022/10/10
- [PATCH v4 23/24] target/arm: Implement FEAT_HAFDBS, dirty bit portion, Richard Henderson, 2022/10/10