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[PATCH v4 15/16] accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_a
From: |
Richard Henderson |
Subject: |
[PATCH v4 15/16] accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8 |
Date: |
Thu, 25 May 2023 17:23:33 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
.../aarch64/host/load-extract-al16-al8.h | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 host/include/aarch64/host/load-extract-al16-al8.h
diff --git a/host/include/aarch64/host/load-extract-al16-al8.h
b/host/include/aarch64/host/load-extract-al16-al8.h
new file mode 100644
index 0000000000..bd677c5e26
--- /dev/null
+++ b/host/include/aarch64/host/load-extract-al16-al8.h
@@ -0,0 +1,40 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Atomic extract 64 from 128-bit, AArch64 version.
+ *
+ * Copyright (C) 2023 Linaro, Ltd.
+ */
+
+#ifndef AARCH64_LOAD_EXTRACT_AL16_AL8_H
+#define AARCH64_LOAD_EXTRACT_AL16_AL8_H
+
+#include "host/cpuinfo.h"
+#include "tcg/debug-assert.h"
+
+/**
+ * load_atom_extract_al16_or_al8:
+ * @pv: host address
+ * @s: object size in bytes, @s <= 8.
+ *
+ * Load @s bytes from @pv, when pv % s != 0. If [p, p+s-1] does not
+ * cross an 16-byte boundary then the access must be 16-byte atomic,
+ * otherwise the access must be 8-byte atomic.
+ */
+static inline uint64_t load_atom_extract_al16_or_al8(void *pv, int s)
+{
+ uintptr_t pi = (uintptr_t)pv;
+ __int128_t *ptr_align = (__int128_t *)(pi & ~7);
+ int shr = (pi & 7) * 8;
+ uint64_t l, h;
+
+ /*
+ * With FEAT_LSE2, LDP is single-copy atomic if 16-byte aligned
+ * and single-copy atomic on the parts if 8-byte aligned.
+ * All we need do is align the pointer mod 8.
+ */
+ tcg_debug_assert(HAVE_ATOMIC128_RO);
+ asm("ldp %0, %1, %2" : "=r"(l), "=r"(h) : "m"(*ptr_align));
+ return (l >> shr) | (h << (-shr & 63));
+}
+
+#endif /* AARCH64_LOAD_EXTRACT_AL16_AL8_H */
--
2.34.1
- [PATCH v4 06/16] tcg/aarch64: Rename temporaries, (continued)
- [PATCH v4 06/16] tcg/aarch64: Rename temporaries, Richard Henderson, 2023/05/25
- [PATCH v4 04/16] qemu/atomic128: Add x86_64 atomic128-ldst.h, Richard Henderson, 2023/05/25
- [PATCH v4 07/16] tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2, Richard Henderson, 2023/05/25
- [PATCH v4 08/16] tcg/aarch64: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/05/25
- [PATCH v4 12/16] accel/tcg: Extract load_atom_extract_al16_or_al8 to host header, Richard Henderson, 2023/05/25
- [PATCH v4 10/16] tcg/ppc: Support 128-bit load/store, Richard Henderson, 2023/05/25
- [PATCH v4 09/16] tcg/aarch64: Support 128-bit load/store, Richard Henderson, 2023/05/25
- [PATCH v4 15/16] accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8,
Richard Henderson <=
- [PATCH v4 16/16] accel/tcg: Add aarch64 store_atom_insert_al16, Richard Henderson, 2023/05/25
- [PATCH v4 13/16] accel/tcg: Extract store_atom_insert_al16 to host header, Richard Henderson, 2023/05/25
- [PATCH v4 14/16] accel/tcg: Add x86_64 load_atom_extract_al16_or_al8, Richard Henderson, 2023/05/25
- [PATCH v4 11/16] tcg/s390x: Support 128-bit load/store, Richard Henderson, 2023/05/25