[Qemu-commits] [qemu/qemu] 34bfe4: target/arm: Move cortex sysregs into

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[Qemu-commits] [qemu/qemu] 34bfe4: target/arm: Move cortex sysregs into

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] 34bfe4: target/arm: Move cortex sysregs into a separate file
Date:	Tue, 02 May 2023 06:06:03 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 34bfe46732e7ddfcc68942f3d41366e147f5cd85
      
https://github.com/qemu/qemu/commit/34bfe46732e7ddfcc68942f3d41366e147f5cd85
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    A target/arm/cortex-regs.c
    M target/arm/cpregs.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/internals.h
    M target/arm/meson.build

  Log Message:
  -----------
  target/arm: Move cortex sysregs into a separate file

The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into a new file.

Also move the function declaration to the more appropriate cpregs.h.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230426180013.14814-2-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 51e41b236266cc5233eb5296e1f1d126ae11adcd
      
https://github.com/qemu/qemu/commit/51e41b236266cc5233eb5296e1f1d126ae11adcd
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Remove dead code from cpu_max_set_sve_max_vq

The sve-max-vq property has been removed from the -cpu max used with
KVM, so code under kvm_enabled in cpu_max_set_sve_max_vq is not
reachable.

Fixes: 0baa21be49 ("target/arm: Make KVM -cpu max exactly like -cpu host")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230426180013.14814-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 25be21059f7562b409bc2253fe2760621e2691bb
      
https://github.com/qemu/qemu/commit/25be21059f7562b409bc2253fe2760621e2691bb
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Extract TCG -cpu max code into a function

Introduce aarch64_max_tcg_initfn that contains the TCG-only part of
-cpu max configuration. We'll need that to be able to restrict this
code to a TCG-only config in the next patches.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230426180013.14814-4-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fcab465e264e18ca74f0513b8f5b682c3362ed7f
      
https://github.com/qemu/qemu/commit/fcab465e264e18ca74f0513b8f5b682c3362ed7f
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Do not expose all -cpu max features to qtests

We're about to move the TCG-only -cpu max configuration code under
CONFIG_TCG. To be able to do that we need to make sure the qtests
still have some cpu configured even when no other accelerator is
available.

Delineate now what is used with TCG-only and what is also used with
qtests to make the subsequent patches cleaner.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230426180013.14814-5-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 39920a04952b67fb1fce8fc3519ac18b7a95f3f3
      
https://github.com/qemu/qemu/commit/39920a04952b67fb1fce8fc3519ac18b7a95f3f3
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/arm/virt.c
    M target/arm/cpu64.c
    M target/arm/internals.h
    A target/arm/tcg/cpu64.c
    M target/arm/tcg/meson.build

  Log Message:
  -----------
  target/arm: Move 64-bit TCG CPUs into tcg/

Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1

Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230426180013.14814-6-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 557ed03a281d845b0a73d56204e91b22982c7c95
      
https://github.com/qemu/qemu/commit/557ed03a281d845b0a73d56204e91b22982c7c95
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M tests/qtest/arm-cpu-features.c

  Log Message:
  -----------
  tests/qtest: Adjust and document query-cpu-model-expansion test for arm

We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the
query-cpu-model-expansion test to check against the cortex-a7, which
is already under CONFIG_TCG. That allows the next patch to contain
only code movement. (All the test cares about is that the CPU type
it's checking is one which definitely doesn't work under KVM.)

While here add comments clarifying what we're testing.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230426180013.14814-7-farosas@suse.de
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 20cf68efcec25b1d95cfe3659aded5314bd1b819
      
https://github.com/qemu/qemu/commit/20cf68efcec25b1d95cfe3659aded5314bd1b819
  Author: Claudio Fontana <cfontana@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/arm/virt.c
    R target/arm/cpu_tcg.c
    M target/arm/meson.build
    A target/arm/tcg/cpu32.c
    M target/arm/tcg/cpu64.c
    M target/arm/tcg/meson.build

  Log Message:
  -----------
  target/arm: move cpu_tcg to tcg/cpu32.c

move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230426180013.14814-8-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0c1ae3ff9dedd8a77bad5508413ccdcfc2493df6
      
https://github.com/qemu/qemu/commit/0c1ae3ff9dedd8a77bad5508413ccdcfc2493df6
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M tests/qtest/bios-tables-test.c
    M tests/qtest/boot-serial-test.c
    M tests/qtest/migration-test.c
    M tests/qtest/pxe-test.c
    M tests/qtest/vmgenid-test.c

  Log Message:
  -----------
  tests/qtest: Fix tests when no KVM or TCG are present

It is possible to have a build with both TCG and KVM disabled due to
Xen requiring the i386 and x86_64 binaries to be present in an aarch64
host.

If we build with --disable-tcg on the aarch64 host, we will end-up
with a QEMU binary (x86) that does not support TCG nor KVM.

Skip tests that crash or hang in the above scenario. Do not include
any test cases if TCG and KVM are missing.

Make sure that calls to qtest_has_accel are placed after g_test_init
in similar fashion to commit ae4b01b349 ("tests: Ensure TAP version is
printed before other messages") to avoid TAP parsing errors.

Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230426180013.14814-9-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 43dc139c71255953237520e19ba5ebd259d24aae
      
https://github.com/qemu/qemu/commit/43dc139c71255953237520e19ba5ebd259d24aae
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M tests/avocado/migration.py

  Log Message:
  -----------
  tests/avocado: Pass parameters to migration test

The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line.

Add a separate class to each architecture so that we can specify
'machine' and 'cpu' options instead of relying on defaults.

Add a skip decorator to keep the current behavior of only running
migration tests when the qemu target matches the host architecture.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230426180013.14814-10-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 99f2f2ad9ee440b50fd33468f234d3287f8a2cfd
      
https://github.com/qemu/qemu/commit/99f2f2ad9ee440b50fd33468f234d3287f8a2cfd
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M configs/devices/arm-softmmu/default.mak
    M hw/arm/Kconfig
    M target/arm/Kconfig

  Log Message:
  -----------
  arm/Kconfig: Always select SEMIHOSTING when TCG is present

We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.

Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect other architectures which might
implement semihosting in a way compatible with KVM.

The selection from ARM_v7M needs to be removed to avoid a cycle during
parsing.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230426180013.14814-11-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 29d9efca16080211f107b540f04d1ed3c12c63b0
      
https://github.com/qemu/qemu/commit/29d9efca16080211f107b540f04d1ed3c12c63b0
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M configs/devices/aarch64-softmmu/default.mak
    M configs/devices/arm-softmmu/default.mak
    M hw/arm/Kconfig

  Log Message:
  -----------
  arm/Kconfig: Do not build TCG-only boards on a KVM-only build

Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.

I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-default.mak. That way we don't surprise anyone that's
used to altering these files.

With this change we can start building with --disable-tcg.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230426180013.14814-12-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: aecca1773fa504d90813b6f5e984f64b4b0f6493
      
https://github.com/qemu/qemu/commit/aecca1773fa504d90813b6f5e984f64b4b0f6493
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M tests/qtest/meson.build

  Log Message:
  -----------
  tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG

The test set -accel tcg, so restrict it to when TCG is present.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230426180013.14814-13-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fd99dd8654c767df01dab28448338ad80e9a2b4d
      
https://github.com/qemu/qemu/commit/fd99dd8654c767df01dab28448338ad80e9a2b4d
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M .gitlab-ci.d/crossbuilds.yml
    M .gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml

  Log Message:
  -----------
  gitlab-ci: Check building KVM-only aarch64 target

Add a manual new job to cross-build the aarch64 target with
only the KVM accelerator enabled (in particular, no TCG).

Re-enable running the similar job on the project Aarch64
custom runner.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230426180013.14814-14-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c94beef9584a5720dd244a37f43ddd8edbf8a9e0
      
https://github.com/qemu/qemu/commit/c94beef9584a5720dd244a37f43ddd8edbf8a9e0
  Author: Patrick Venture <venture@google.com>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/net/npcm7xx_emc.c

  Log Message:
  -----------
  hw/net: npcm7xx_emc: set MAC in register space

The MAC address set from Qemu wasn't being saved into the register space.

Reviewed-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: moved variable declaration to top of function]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 007d567d180fa4e62f864c2bc2a3d16fad78ad1f
      
https://github.com/qemu/qemu/commit/007d567d180fa4e62f864c2bc2a3d16fad78ad1f
  Author: Daniel Bertalan <dani@danielbertalan.dev>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/bcm2836.c
    M hw/arm/raspi.c
    M hw/misc/bcm2835_property.c
    M include/hw/misc/bcm2835_property.h

  Log Message:
  -----------
  hw/arm/bcm2835_property: Implement "get command line" message

This query copies the kernel command line into the message buffer. It
was previously stubbed out to return empty, this commit makes it reflect
the arguments specified with `-append`.

I observed the following peculiarities on my Pi 3B+:
- If the buffer is shorter than the string, the response header gives
  the full length, but no data is actually copied.
- No NUL terminator is added: even if the buffer is long enough to fit
  one, the buffer's original contents are preserved past the string's
  end.
- The VC firmware adds the following extra parameters beside the
  user-supplied ones (via /boot/cmdline.txt): `video`, `vc_mem.mem_base`
  and `vc_mem.mem_size`. This is currently not implemented in qemu.

Signed-off-by: Daniel Bertalan <dani@danielbertalan.dev>
Message-id: 20230425103250.56653-1-dani@danielbertalan.dev
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: added comment about NUL and short-buffer behaviour]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1779bb42c13875f04b5a05d306e3aba3a51489e8
      
https://github.com/qemu/qemu/commit/1779bb42c13875f04b5a05d306e3aba3a51489e8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M accel/tcg/tcg-all.c
    M bsd-user/main.c
    M linux-user/main.c
    M qemu-options.hx
    M softmmu/vl.c

  Log Message:
  -----------
  make one-insn-per-tb an accel option

This commit adds 'one-insn-per-tb' as a property on the TCG
accelerator object, so you can enable it with
   -accel tcg,one-insn-per-tb=on

It has the same behaviour as the existing '-singlestep' command line
option.  We use a different name because 'singlestep' has always been
a confusing choice, because it doesn't have anything to do with
single-stepping the CPU.  What it does do is force TCG emulation to
put one guest instruction in each TB, which can be useful in some
situations (such as analysing debug logs).

The existing '-singlestep' commandline options are decoupled from the
global 'singlestep' variable and instead now are syntactic sugar for
setting the accel property.  (These can then go away after a
deprecation period.)

The global variable remains for the moment as:
 * what the TCG code looks at to change its behaviour
 * what HMP and QMP use to query and set the behaviour

In the following commits we'll clean those up to not directly
look at the global variable.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230417164041.684562-2-peter.maydell@linaro.org


  Commit: 16566c310dbba34c711bc43db467e17a92d4fbd4
      
https://github.com/qemu/qemu/commit/16566c310dbba34c711bc43db467e17a92d4fbd4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M softmmu/runstate-hmp-cmds.c
    M softmmu/runstate.c

  Log Message:
  -----------
  softmmu: Don't use 'singlestep' global in QMP and HMP commands

The HMP 'singlestep' command, the QMP 'query-status' command and the
HMP 'info status' command (which is just wrapping the QMP command
implementation) look at the 'singlestep' global variable. Make them
access the new TCG accelerator 'one-insn-per-tb' property instead.

This leaves the HMP and QMP command/field names and output strings
unchanged; we will clean that up later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230417164041.684562-3-peter.maydell@linaro.org


  Commit: eabb1613e732acf7d6a4ceffc26fd2e3fb43c20b
      
https://github.com/qemu/qemu/commit/eabb1613e732acf7d6a4ceffc26fd2e3fb43c20b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M accel/tcg/internal.h
    M accel/tcg/tcg-all.c
    M bsd-user/main.c
    M include/exec/cpu-common.h
    M linux-user/main.c
    M softmmu/globals.c

  Log Message:
  -----------
  accel/tcg: Use one_insn_per_tb global instead of old singlestep global

The only place left that looks at the old 'singlestep' global
variable is the TCG curr_cflags() function.  Replace the old global
with a new 'one_insn_per_tb' which is defined in tcg-all.c and
declared in accel/tcg/internal.h.  This keeps it restricted to the
TCG code, unlike 'singlestep' which was available to every file in
the system and defined in multiple different places for softmmu vs
linux-user vs bsd-user.

While we're making this change, use qatomic_read() and qatomic_set()
on the accesses to the new global, because TCG will read it without
holding a lock.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230417164041.684562-4-peter.maydell@linaro.org


  Commit: 82120f48e3657227e4780c50acc4e2295c534a34
      
https://github.com/qemu/qemu/commit/82120f48e3657227e4780c50acc4e2295c534a34
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M docs/user/main.rst
    M linux-user/main.c

  Log Message:
  -----------
  linux-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'

The '-singlestep' option is confusing, because it doesn't actually
have anything to do with single-stepping the CPU. What it does do
is force TCG emulation to put one guest instruction in each TB,
which can be useful in some situations.

Create a new command line argument -one-insn-per-tb, so we can
document that -singlestep is just a deprecated synonym for it,
and eventually perhaps drop it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230417164041.684562-5-peter.maydell@linaro.org


  Commit: 5faa452016b3f15451ede90420cb914d077f4cb7
      
https://github.com/qemu/qemu/commit/5faa452016b3f15451ede90420cb914d077f4cb7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M bsd-user/main.c
    M docs/user/main.rst

  Log Message:
  -----------
  bsd-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'

The '-singlestep' option is confusing, because it doesn't actually
have anything to do with single-stepping the CPU. What it does do
is force TCG emulation to put one guest instruction in each TB,
which can be useful in some situations.

Create a new command line argument -one-insn-per-tb, so we can
document that -singlestep is just a deprecated synonym for it,
and eventually perhaps drop it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230417164041.684562-6-peter.maydell@linaro.org


  Commit: be69037d230be585188a74b1a9ef1a3bda0e1839
      
https://github.com/qemu/qemu/commit/be69037d230be585188a74b1a9ef1a3bda0e1839
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M docs/about/deprecated.rst
    M qemu-options.hx
    M tcg/tci/README

  Log Message:
  -----------
  Document that -singlestep command line option is deprecated

Document that the -singlestep command line option is now
deprecated, as it is replaced by either the TCG accelerator
property 'one-insn-per-tb' for system emulation or the new
'-one-insn-per-tb' option for usermode emulation, and remove
the only use of the deprecated syntax from a README.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230417164041.684562-7-peter.maydell@linaro.org


  Commit: 3d0370bddbb8fb5c811aed04fb40c71e72a96c86
      
https://github.com/qemu/qemu/commit/3d0370bddbb8fb5c811aed04fb40c71e72a96c86
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M accel/tcg/monitor.c
    M softmmu/runstate-hmp-cmds.c

  Log Message:
  -----------
  accel/tcg: Report one-insn-per-tb in 'info jit', not 'info status'

Currently we report whether the TCG accelerator is in
'one-insn-per-tb' mode in the 'info status' output.  This is a pretty
minor piece of TCG specific information, and we want to deprecate the
'singlestep' field of the associated QMP command.  Move the
'one-insn-per-tb' reporting to 'info jit'.

We don't need a deprecate-and-drop period for this because the
HMP interface has no stability guarantees.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230417164041.684562-8-peter.maydell@linaro.org


  Commit: bab1611b6b4cbaa3963d8aca5987d143a87ac320
      
https://github.com/qemu/qemu/commit/bab1611b6b4cbaa3963d8aca5987d143a87ac320
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M docs/about/deprecated.rst
    M hmp-commands.hx
    M include/monitor/hmp.h
    M softmmu/runstate-hmp-cmds.c
    M tests/qtest/test-hmp.c

  Log Message:
  -----------
  hmp: Add 'one-insn-per-tb' command equivalent to 'singlestep'

The 'singlestep' HMP command is confusing, because it doesn't
actually have anything to do with single-stepping the CPU.  What it
does do is force TCG emulation to put one guest instruction in each
TB, which can be useful in some situations.

Create a new HMP command  'one-insn-per-tb', so we can document that
'singlestep' is just a deprecated synonym for it, and eventually
perhaps drop it.

We aren't obliged to do deprecate-and-drop for HMP commands,
but it's easy enough to do so, so we do.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230417164041.684562-9-peter.maydell@linaro.org


  Commit: 6d916baa6b4e5dbaedec4941cfcc83ac0d5d0196
      
https://github.com/qemu/qemu/commit/6d916baa6b4e5dbaedec4941cfcc83ac0d5d0196
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M qapi/run-state.json

  Log Message:
  -----------
  qapi/run-state.json: Fix missing newline at end of file

The run-state.json file is missing a trailing newline; add it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230417164041.684562-10-peter.maydell@linaro.org


  Commit: c5ecfb8245021ad220236874373022d6dee0bb7e
      
https://github.com/qemu/qemu/commit/c5ecfb8245021ad220236874373022d6dee0bb7e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M docs/about/deprecated.rst
    M qapi/run-state.json

  Log Message:
  -----------
  qmp: Deprecate 'singlestep' member of StatusInfo

The 'singlestep' member of StatusInfo has never done what the QMP
documentation claims it does.  What it actually reports is whether
TCG is working in "one guest instruction per translation block" mode.

We no longer need this field for the HMP 'info status' command, as
we've moved that information to 'info jit'.  It seems unlikely that
anybody is monitoring the state of this obscure TCG setting via QMP,
especially since QMP provides no means for changing the setting.  So
simply deprecate the field, without providing any replacement.

Until we do eventually delete the member, correct the misstatements
in the QAPI documentation about it.

If we do find that there are users for this, then the most likely way
we would provide replacement access to the information would be to
put the accelerator QOM object at a well-known path such as
/machine/accel, which could then be used with the existing qom-set
and qom-get commands.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-id: 20230417164041.684562-11-peter.maydell@linaro.org


  Commit: 55471c082c8a848b25a4e32b7140aa3041893ed2
      
https://github.com/qemu/qemu/commit/55471c082c8a848b25a4e32b7140aa3041893ed2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M docs/about/deprecated.rst

  Log Message:
  -----------
  docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation

In commit 5242876f37ca we deprecated the dtb-kaslr-seed property of
the virt board, but forgot the "since n.n" tag in the documentation
of this in deprecated.rst.

This deprecation note first appeared in the 7.1 release, so
retrospectively add the correct "since 7.1" annotation to it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230420122256.1023709-1-peter.maydell@linaro.org


  Commit: 9709164bc18c46239b063b3cbb79b2248e4489a9
      
https://github.com/qemu/qemu/commit/9709164bc18c46239b063b3cbb79b2248e4489a9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/net/msf2-emac.c

  Log Message:
  -----------
  hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc()

The msf2-emac ethernet controller has functions emac_load_desc() and
emac_store_desc() which read and write the in-memory descriptor
blocks and handle conversion between guest and host endianness.

As currently written, emac_store_desc() does the endianness
conversion in-place; this means that it effectively consumes the
input EmacDesc struct, because on a big-endian host the fields will
be overwritten with the little-endian versions of their values.
Unfortunately, in all the callsites the code continues to access
fields in the EmacDesc struct after it has called emac_store_desc()
-- specifically, it looks at the d.next field.

The effect of this is that on a big-endian host networking doesn't
work because the address of the next descriptor is corrupted.

We could fix this by making the callsite avoid using the struct; but
it's more robust to have emac_store_desc() leave its input alone.

(emac_load_desc() also does an in-place conversion, but here this is
fine, because the function is supposed to be initializing the
struct.)

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230424151919.1333299-1-peter.maydell@linaro.org


  Commit: 254456fd63f037ecdbc0000f5a82e03957b84f67
      
https://github.com/qemu/qemu/commit/254456fd63f037ecdbc0000f5a82e03957b84f67
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/arm/boot.c
    M include/hw/arm/boot.h

  Log Message:
  -----------
  hw/arm/boot: Make write_bootloader() public as arm_write_bootloader()

The arm boot.c code includes a utility function write_bootloader()
which assists in writing a boot-code fragment into guest memory,
including handling endianness and fixing it up with entry point
addresses and similar things.  This is useful not just for the boot.c
code but also in board model code, so rename it to
arm_write_bootloader() and make it globally visible.

Since we are making it public, make its API a little neater: move the
AddressSpace* argument to be next to the hwaddr argument, and allow
the fixupcontext array to be const, since we never modify it in this
function.

Cc: qemu-stable@nongnu.org
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230424152717.1333930-2-peter.maydell@linaro.org
[PMM: Split out from another patch by Cédric, added doc comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: abbc39843ee96612973b031fb219a17e37beb3d5
      
https://github.com/qemu/qemu/commit/abbc39843ee96612973b031fb219a17e37beb3d5
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw/arm/aspeed: Use arm_write_bootloader() to write the bootloader

When writing the secondary-CPU stub boot loader code to the guest,
use arm_write_bootloader() instead of directly calling
rom_add_blob_fixed().  This fixes a bug on big-endian hosts, because
arm_write_bootloader() will correctly byte-swap the host-byte-order
array values into the guest-byte-order to write into the guest
memory.

Cc: qemu-stable@nongnu.org
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230424152717.1333930-3-peter.maydell@linaro.org
[PMM: Moved the "make arm_write_bootloader() function public" part
 to its own patch; updated commit message to note that this fixes
 an actual bug; adjust to the API changes noted in previous commit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ece7d6201f41bfa77fee47a126231b575689313f
      
https://github.com/qemu/qemu/commit/ece7d6201f41bfa77fee47a126231b575689313f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Use arm_write_bootloader() to write boot code

When writing the secondary-CPU stub boot loader code to the guest,
use arm_write_bootloader() instead of directly calling
rom_add_blob_fixed().  This fixes a bug on big-endian hosts, because
arm_write_bootloader() will correctly byte-swap the host-byte-order
array values into the guest-byte-order to write into the guest
memory.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230424152717.1333930-4-peter.maydell@linaro.org


  Commit: dabd8ce5a34e000b4d39dc0287d97cd26d9cc84b
      
https://github.com/qemu/qemu/commit/dabd8ce5a34e000b4d39dc0287d97cd26d9cc84b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/intc/allwinner-a10-pic.c

  Log Message:
  -----------
  hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()

The Allwinner PIC model uses set_bit() and clear_bit() to update the
values in its irq_pending[] array when an interrupt arrives.  However
it is using these functions wrongly: they work on an array of type
'long', and it is passing an array of type 'uint32_t'.  Because the
code manually figures out the right array element, this works on
little-endian hosts and on 32-bit big-endian hosts, where bits 0..31
in a 'long' are in the same place as they are in a 'uint32_t'.
However it breaks on 64-bit big-endian hosts.

Remove the use of set_bit() and clear_bit() in favour of using
deposit32() on the array element.  This fixes a bug where on
big-endian 64-bit hosts the guest kernel would hang early on in
bootup.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230424152833.1334136-1-peter.maydell@linaro.org


  Commit: 562f2a18931efd17154444fa5ee0e7486a03fcaf
      
https://github.com/qemu/qemu/commit/562f2a18931efd17154444fa5ee0e7486a03fcaf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M target/arm/tcg/translate.c
    M target/arm/translate-a32.h

  Log Message:
  -----------
  target/arm: Define and use new load_cpu_field_low32()

In several places in the 32-bit Arm translate.c, we try to use
load_cpu_field() to load from a CPUARMState field into a TCGv_i32
where the field is actually 64-bit. This works on little-endian
hosts, but gives the wrong half of the register on big-endian.

Add a new load_cpu_field_low32() which loads the low 32 bits
of a 64-bit field into a TCGv_i32. The new macro includes a
compile-time check against accidentally using it on a field
of the wrong size. Use it to fix the two places in the code
where we were using load_cpu_field() on a 64-bit field.

This fixes a bug where on big-endian hosts the guest would
crash after executing an ERET instruction, and a more corner
case one where some UNDEFs for attempted accesses to MSR
banked registers from Secure EL1 might go to the wrong EL.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230424153909.1419369-2-peter.maydell@linaro.org


  Commit: 2a625f6402c2c68ff346e6de06e42ec8dcad8c0f
      
https://github.com/qemu/qemu/commit/2a625f6402c2c68ff346e6de06e42ec8dcad8c0f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M target/arm/translate-a32.h

  Log Message:
  -----------
  target/arm: Add compile time asserts to load/store_cpu_field macros

Add some compile-time asserts to the load_cpu_field() and store_cpu_field()
macros that the struct field being accessed is the expected size. This
lets us catch cases where we incorrectly tried to do a 32-bit load
from a 64-bit struct field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230424153909.1419369-3-peter.maydell@linaro.org


  Commit: 3098098c2b0d5c141ae2459a97bd5b88682d0a3f
      
https://github.com/qemu/qemu/commit/3098098c2b0d5c141ae2459a97bd5b88682d0a3f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/sd/allwinner-sdhost.c

  Log Message:
  -----------
  hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields

In allwinner_sdhost_process_desc() we just read directly from
guest memory into a host TransferDescriptor struct and back.
This only works on little-endian hosts. Abstract the reading
and writing of descriptors into functions that handle the
byte-swapping so that TransferDescriptor structs as seen by
the rest of the code are always in host-order.

This fixes a failure of one of the avocado tests on s390.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230424165053.1428857-2-peter.maydell@linaro.org


  Commit: 0ab99e4252f21550f2c16f859cbcdd3cced9f8bf
      
https://github.com/qemu/qemu/commit/0ab99e4252f21550f2c16f859cbcdd3cced9f8bf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M hw/net/allwinner-sun8i-emac.c

  Log Message:
  -----------
  hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields

In allwinner-sun8i-emac we just read directly from guest memory into
a host FrameDescriptor struct and back.  This only works on
little-endian hosts.  Reading and writing of descriptors is already
abstracted into functions; make those functions also handle the
byte-swapping so that TransferDescriptor structs as seen by the rest
of the code are always in host-order, and fix two places that were
doing ad-hoc descriptor reading without using the functions.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230424165053.1428857-3-peter.maydell@linaro.org


  Commit: 1153be44bf406a2c468e69e7d717a8bd5a507b51
      
https://github.com/qemu/qemu/commit/1153be44bf406a2c468e69e7d717a8bd5a507b51
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M .gitlab-ci.d/crossbuilds.yml
    M .gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
    M accel/tcg/cpu-exec.c
    M accel/tcg/internal.h
    M accel/tcg/monitor.c
    M accel/tcg/tcg-all.c
    M bsd-user/main.c
    M configs/devices/aarch64-softmmu/default.mak
    M configs/devices/arm-softmmu/default.mak
    M docs/about/deprecated.rst
    M docs/user/main.rst
    M hmp-commands.hx
    M hw/arm/Kconfig
    M hw/arm/aspeed.c
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/bcm2836.c
    M hw/arm/boot.c
    M hw/arm/raspi.c
    M hw/arm/virt.c
    M hw/intc/allwinner-a10-pic.c
    M hw/misc/bcm2835_property.c
    M hw/net/allwinner-sun8i-emac.c
    M hw/net/msf2-emac.c
    M hw/net/npcm7xx_emc.c
    M hw/sd/allwinner-sdhost.c
    M include/exec/cpu-common.h
    M include/hw/arm/boot.h
    M include/hw/misc/bcm2835_property.h
    M include/monitor/hmp.h
    M linux-user/main.c
    M qapi/run-state.json
    M qemu-options.hx
    M softmmu/globals.c
    M softmmu/runstate-hmp-cmds.c
    M softmmu/runstate.c
    M softmmu/vl.c
    M target/arm/Kconfig
    A target/arm/cortex-regs.c
    M target/arm/cpregs.h
    M target/arm/cpu64.c
    R target/arm/cpu_tcg.c
    M target/arm/internals.h
    M target/arm/meson.build
    A target/arm/tcg/cpu32.c
    A target/arm/tcg/cpu64.c
    M target/arm/tcg/meson.build
    M target/arm/tcg/translate.c
    M target/arm/translate-a32.h
    M tcg/tci/README
    M tests/avocado/migration.py
    M tests/qtest/arm-cpu-features.c
    M tests/qtest/bios-tables-test.c
    M tests/qtest/boot-serial-test.c
    M tests/qtest/migration-test.c
    M tests/qtest/pxe-test.c
    M tests/qtest/test-hmp.c
    M tests/qtest/vmgenid-test.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20230502-1' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

 * Support building Arm targets with CONFIG_TCG=no (ie KVM only)
 * hw/net: npcm7xx_emc: set MAC in register space
 * hw/arm/bcm2835_property: Implement "get command line" message
 * Deprecate the '-singlestep' command line option in favour of
   '-one-insn-per-tb' and '-accel one-insn-per-tb=on'
 * Deprecate 'singlestep' member of QMP StatusInfo struct
 * docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation
 * hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc()
 * raspi, aspeed: Write bootloader code correctly on big-endian hosts
 * hw/intc/allwinner-a10-pic: Fix bug on big-endian hosts
 * Fix bug in A32 ERET on big-endian hosts that caused guest crash
 * hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields
 * hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields

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# gpg: Signature made Tue 02 May 2023 01:11:24 PM BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20230502-1' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (35 commits)
  hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields
  hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields
  target/arm: Add compile time asserts to load/store_cpu_field macros
  target/arm: Define and use new load_cpu_field_low32()
  hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()
  hw/arm/raspi: Use arm_write_bootloader() to write boot code
  hw/arm/aspeed: Use arm_write_bootloader() to write the bootloader
  hw/arm/boot: Make write_bootloader() public as arm_write_bootloader()
  hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc()
  docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation
  qmp: Deprecate 'singlestep' member of StatusInfo
  qapi/run-state.json: Fix missing newline at end of file
  hmp: Add 'one-insn-per-tb' command equivalent to 'singlestep'
  accel/tcg: Report one-insn-per-tb in 'info jit', not 'info status'
  Document that -singlestep command line option is deprecated
  bsd-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'
  linux-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'
  accel/tcg: Use one_insn_per_tb global instead of old singlestep global
  softmmu: Don't use 'singlestep' global in QMP and HMP commands
  make one-insn-per-tb an accel option
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/1b0e90a87b46...1153be44bf40
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