[Qemu-commits] [qemu/qemu] 6a6447: softmmu: Tidy dirtylimit_dirty_ring

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[Qemu-commits] [qemu/qemu] 6a6447: softmmu: Tidy dirtylimit_dirty_ring_f

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] 6a6447: softmmu: Tidy dirtylimit_dirty_ring_full_time
Date:	Tue, 02 May 2023 23:26:33 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6a6447fe252e2f1c48d6e8cc1bd36515852e8040
      
https://github.com/qemu/qemu/commit/6a6447fe252e2f1c48d6e8cc1bd36515852e8040
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M softmmu/dirtylimit.c

  Log Message:
  -----------
  softmmu: Tidy dirtylimit_dirty_ring_full_time

Drop inline marker: let compiler decide.

Change return type to uint64_t: this matches the computation in the
return statement and the local variable assignment in the caller.

Rename local to dirty_ring_size_MB to fix typo.
Simplify conversion to MiB via qemu_target_page_bits and right shift.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ac01ec6fe59458978b32624a6e93b5f2e55b593f
      
https://github.com/qemu/qemu/commit/ac01ec6fe59458978b32624a6e93b5f2e55b593f
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Uncache the host address for instruction fetch when tlb size < 1

When PMP entry overlap part of the page, we'll set the tlb_size to 1, which
will make the address in tlb entry set with TLB_INVALID_MASK, and the next
access will again go through tlb_fill.However, this way will not work in
tb_gen_code() => get_page_addr_code_hostp(): the TLB host address will be
cached, and the following instructions can use this host address directly
which may lead to the bypass of PMP related check.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1542.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230422130329.23555-6-liweiwei@iscas.ac.cn>


  Commit: 8841c815a93a2da3e60fb8173d9c5dc01f552dab
      
https://github.com/qemu/qemu/commit/8841c815a93a2da3e60fb8173d9c5dc01f552dab
  Author: Dickon Hood <dickon.hood@codethink.co.uk>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M include/qemu/bitops.h

  Log Message:
  -----------
  qemu/bitops.h: Limit rotate amounts

Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.)  This fixes a problem with riscv
vector rotate instructions.

Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
[rth: Mask shifts in both directions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 31fe256d32d70c83232c68c6e2d136b533e1dda0
      
https://github.com/qemu/qemu/commit/31fe256d32d70c83232c68c6e2d136b533e1dda0
  Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M include/qemu/host-utils.h

  Log Message:
  -----------
  qemu/host-utils.h: Add clz and ctz functions for lower-bit integers

This is for use in the RISC-V vclz and vctz instructions (implemented in
proceeding commit).

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-11-lawrence.hunter@codethink.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4221aa4a882403fc7d6d22ad6af9a58c8a5badf6
      
https://github.com/qemu/qemu/commit/4221aa4a882403fc7d6d22ad6af9a58c8a5badf6
  Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M include/tcg/tcg-op-gvec.h
    M tcg/tcg-op-gvec.c

  Log Message:
  -----------
  tcg: Add tcg_gen_gvec_andcs

Add tcg expander and helper functions for and-compliment
vector with scalar operand.

Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk>
[rth: Split out of larger patch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bef317d0c36d66cb44d14a0838d5abe7b26b0344
      
https://github.com/qemu/qemu/commit/bef317d0c36d66cb44d14a0838d5abe7b26b0344
  Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M include/tcg/tcg-op-gvec.h
    M tcg/tcg-op-gvec.c

  Log Message:
  -----------
  tcg: Add tcg_gen_gvec_rotrs

Add tcg expander and helper functions for rotate right
vector with scalar operand.

Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk>
[rth: Split out of larger patch; mask rotation count.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c4075353854ed320cf9225ebd5605836ae236640
      
https://github.com/qemu/qemu/commit/c4075353854ed320cf9225ebd5605836ae236640
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M include/qemu/int128.h

  Log Message:
  -----------
  qemu/int128: Re-shuffle Int128Alias members

Clang 14, with --enable-tcg-interpreter errors with

include/qemu/int128.h:487:16: error: alignment of field 'i' (128 bits)
  does not match the alignment of the first field in transparent union;
  transparent_union attribute ignored [-Werror,-Wignored-attributes]
    __int128_t i;
               ^
include/qemu/int128.h:486:12: note: alignment of first field is 64 bits
    Int128 s;
           ^
1 error generated.

By placing the __uint128_t member first, this is avoided.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230501204625.277361-1-richard.henderson@linaro.org>


  Commit: dc165fcd4effb9e005a4514ab7d666322648e971
      
https://github.com/qemu/qemu/commit/dc165fcd4effb9e005a4514ab7d666322648e971
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M meson.build
    M migration/xbzrle.c

  Log Message:
  -----------
  migration/xbzrle: Use __attribute__((target)) for avx512

Use the attribute, which is supported by clang, instead of
the #pragma, which is not supported and, for some reason,
also not detected by the meson probe, so we fail by -Werror.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20230501210555.289806-1-richard.henderson@linaro.org>


  Commit: 2899062614ab68ffcd034909b5ea993d8403d6d6
      
https://github.com/qemu/qemu/commit/2899062614ab68ffcd034909b5ea993d8403d6d6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M include/exec/cpu_ldst.h

  Log Message:
  -----------
  accel/tcg: Add cpu_ld*_code_mmu

At least RISC-V has the need to be able to perform a read
using execute permissions, outside of translation.
Add helpers to facilitate this.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-9-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-9-richard.henderson@linaro.org>


  Commit: 341ac0a05509de103f26e8819b5fecea887f5413
      
https://github.com/qemu/qemu/commit/341ac0a05509de103f26e8819b5fecea887f5413
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64

Since TCG_TYPE_I32 values are kept sign-extended in registers,
via ".w" instructions, we need not extend if the register matches.
This is already relied upon by comparisons.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c6a98619f7179a3564008ea9c9b3672821a6812f
      
https://github.com/qemu/qemu/commit/c6a98619f7179a3564008ea9c9b3672821a6812f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Conditionalize tcg_out_exts_i32_i64

Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not
extend if the register matches.  This is already relied upon by comparisons.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 129f1f9ee7df77d367d961b3c25353612d33cd83
      
https://github.com/qemu/qemu/commit/129f1f9ee7df77d367d961b3c25353612d33cd83
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Introduce tcg_out_movext2

This is common code in most qemu_{ld,st} slow paths, moving two
registers when there may be overlap between sources and destinations.
At present, this is only used by 32-bit hosts for 64-bit data,
but will shortly be used for more than that.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4ebc33f3f3b656ebf62112daca6aa0f8019b4891
      
https://github.com/qemu/qemu/commit/4ebc33f3f3b656ebf62112daca6aa0f8019b4891
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M accel/tcg/user-exec.c
    M include/exec/cpu_ldst.h
    M include/qemu/bitops.h
    M include/qemu/host-utils.h
    M include/qemu/int128.h
    M include/tcg/tcg-op-gvec.h
    M meson.build
    M migration/xbzrle.c
    M softmmu/dirtylimit.c
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/tcg-op-gvec.c
    M tcg/tcg.c

  Log Message:
  -----------
  Merge tag 'pull-tcg-20230502-2' of https://gitlab.com/rth7680/qemu into 
staging

Misc tcg-related patch queue.

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[ultimate]

* tag 'pull-tcg-20230502-2' of https://gitlab.com/rth7680/qemu:
  tcg: Introduce tcg_out_movext2
  tcg/mips: Conditionalize tcg_out_exts_i32_i64
  tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
  accel/tcg: Add cpu_ld*_code_mmu
  migration/xbzrle: Use __attribute__((target)) for avx512
  qemu/int128: Re-shuffle Int128Alias members
  tcg: Add tcg_gen_gvec_rotrs
  tcg: Add tcg_gen_gvec_andcs
  qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
  qemu/bitops.h: Limit rotate amounts
  accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
  softmmu: Tidy dirtylimit_dirty_ring_full_time

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


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