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[Qemu-commits] [qemu/qemu] 24a4d5: accel/tcg: Move HMP info jit and info
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] 24a4d5: accel/tcg: Move HMP info jit and info opcount code |
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Date: |
Mon, 06 Nov 2023 19:08:54 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 24a4d59aa7fdc337eef1c2b589478ea998e54373
https://github.com/qemu/qemu/commit/24a4d59aa7fdc337eef1c2b589478ea998e54373
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/internal-common.h
M accel/tcg/monitor.c
M accel/tcg/translate-all.c
M include/exec/cputlb.h
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
accel/tcg: Move HMP info jit and info opcount code
Move all of it into accel/tcg/monitor.c. This puts everything
about tcg that is only used by the monitor in the same place.
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fa645b48d3da093165406dce2c36f967fac6bd9d
https://github.com/qemu/qemu/commit/fa645b48d3da093165406dce2c36f967fac6bd9d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Add C_N2_I1
Constraint with two outputs, both in new registers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiajie Chen <c@jia.je>
Message-Id: <20230916220151.526140-2-richard.henderson@linaro.org>
Commit: 2b2ae0a42e67a85273c0976466f1a634ede084dc
https://github.com/qemu/qemu/commit/2b2ae0a42e67a85273c0976466f1a634ede084dc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128
Use new registers for the output, so that we never overlap
the input address, which could happen for user-only.
This avoids a "tmp = addr + 0" in that case.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiajie Chen <c@jia.je>
Message-Id: <20230916220151.526140-3-richard.henderson@linaro.org>
Commit: 0885f1221e0add5529dada1e7948d2c00189cb8b
https://github.com/qemu/qemu/commit/0885f1221e0add5529dada1e7948d2c00189cb8b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
A host/include/loongarch64/host/cpuinfo.h
A util/cpuinfo-loongarch.c
M util/meson.build
Log Message:
-----------
util: Add cpuinfo for loongarch64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiajie Chen <c@jia.je>
Message-Id: <20230916220151.526140-4-richard.henderson@linaro.org>
Commit: f2a553481e520e359f735ea6f4a9435e52b3b446
https://github.com/qemu/qemu/commit/f2a553481e520e359f735ea6f4a9435e52b3b446
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
Log Message:
-----------
tcg/loongarch64: Use cpuinfo.h
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiajie Chen <c@jia.je>
Message-Id: <20230916220151.526140-5-richard.henderson@linaro.org>
Commit: adc8467e697db988878cec645ae52aa6b51ce4c4
https://github.com/qemu/qemu/commit/adc8467e697db988878cec645ae52aa6b51ce4c4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
A host/include/loongarch64/host/atomic128-ldst.h
A host/include/loongarch64/host/load-extract-al16-al8.h
A host/include/loongarch64/host/store-insert-al16.h
Log Message:
-----------
host/include/loongarch64: Add atomic16 load and store
While loongarch64 does not have a 128-bit cmpxchg, it does
have 128-bit atomic load and store via the vector unit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230916220151.526140-6-richard.henderson@linaro.org>
Commit: 8b1b3db71a1df58a6e28956b72f143e8cf38bdf6
https://github.com/qemu/qemu/commit/8b1b3db71a1df58a6e28956b72f143e8cf38bdf6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M accel/tcg/ldst_atomicity.c.inc
Log Message:
-----------
accel/tcg: Remove redundant case in store_atom_16
We handled the HAVE_ATOMIC128_RW case with atomic16_set at the top of
the function; the only thing left for a host without that support is
to fall through to cpu_loop_exit_atomic.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230916220151.526140-7-richard.henderson@linaro.org>
Commit: 6046f6e94d8d530ecc28176232479889abbee47e
https://github.com/qemu/qemu/commit/6046f6e94d8d530ecc28176232479889abbee47e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/ldst_atomicity.c.inc
Log Message:
-----------
accel/tcg: Fix condition for store_atom_insert_al16
Store bytes under a mask is fundamentally a cmpxchg, not a straight store.
Use HAVE_CMPXCHG128 instead of HAVE_ATOMIC128_RW.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230916220151.526140-8-richard.henderson@linaro.org>
Commit: ecfa1877f7e9d300b57492552afed2932ed954d7
https://github.com/qemu/qemu/commit/ecfa1877f7e9d300b57492552afed2932ed954d7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Mark tcg_gen_op* as noinline
Encourage the compiler to tail-call rather than inline
across the dozens of opcode expanders.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-2-richard.henderson@linaro.org>
Commit: 6fc75d50a58bdf15fcc09e89880ba5125d572a6d
https://github.com/qemu/qemu/commit/6fc75d50a58bdf15fcc09e89880ba5125d572a6d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Move tcg_gen_op* out of line
In addition to moving out of line, with CONFIG_DEBUG_TCG
mark them all noinline.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-3-richard.henderson@linaro.org>
Commit: 01bbb6e3eb3368b40384a7e044c9a2d342b8039b
https://github.com/qemu/qemu/commit/01bbb6e3eb3368b40384a7e044c9a2d342b8039b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Move generic expanders out of line
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-4-richard.henderson@linaro.org>
Commit: 09607d35f5a9a6aa1c57302c1e27066ad2309e63
https://github.com/qemu/qemu/commit/09607d35f5a9a6aa1c57302c1e27066ad2309e63
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Move 32-bit expanders out of line
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-5-richard.henderson@linaro.org>
Commit: e0de2f558067400e32fc1082468c0664314f3b34
https://github.com/qemu/qemu/commit/e0de2f558067400e32fc1082468c0664314f3b34
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Move 64-bit expanders out of line
This one is more complicated, combining 32-bit and 64-bit
expansion with C if instead of preprocessor #if.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-6-richard.henderson@linaro.org>
Commit: 27c758fd22a825783228dbdd339fd55da08a5ff3
https://github.com/qemu/qemu/commit/27c758fd22a825783228dbdd339fd55da08a5ff3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M tcg/tcg-internal.h
Log Message:
-----------
tcg: Move vec_gen_* declarations to tcg-internal.h
These are used within tcg-op-vec.c and tcg/host/tcg-target.c.inc.
There are no uses outside tcg/.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-7-richard.henderson@linaro.org>
Commit: 1d67bf545fd6321d14150eac00851782073a17e9
https://github.com/qemu/qemu/commit/1d67bf545fd6321d14150eac00851782073a17e9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M tcg/tcg-internal.h
Log Message:
-----------
tcg: Move tcg_gen_opN declarations to tcg-internal.h
These are used within tcg-op.c and tcg-op-ldst.c.
There are no uses outside tcg/.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-8-richard.henderson@linaro.org>
Commit: 17b9fadb1d93edd79ac1aec7f48b66ceff325cbd
https://github.com/qemu/qemu/commit/17b9fadb1d93edd79ac1aec7f48b66ceff325cbd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Unexport tcg_gen_op*_{i32,i64}
These functions are no longer used outside tcg-op.c.
There are several that are completely unused, so remove them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-9-richard.henderson@linaro.org>
Commit: 16edaee720139892dbff97cfcb89bf18eb70d227
https://github.com/qemu/qemu/commit/16edaee720139892dbff97cfcb89bf18eb70d227
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M include/tcg/tcg.h
M tcg/tcg-internal.h
M tcg/tcg.c
Log Message:
-----------
tcg: Move tcg_constant_* out of line
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-10-richard.henderson@linaro.org>
Commit: 4643f3e07edd82f55788d55d30f58239c5468e6f
https://github.com/qemu/qemu/commit/4643f3e07edd82f55788d55d30f58239c5468e6f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-op-common.h
M include/tcg/tcg-temp-internal.h
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-11-richard.henderson@linaro.org>
Commit: 58b797130c659ca084ad298e92ad4ee114c37a06
https://github.com/qemu/qemu/commit/58b797130c659ca084ad298e92ad4ee114c37a06
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-temp-internal.h
M tcg/tcg.c
Log Message:
-----------
tcg: Move tcg_temp_free_* out of line
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231029210848.78234-12-richard.henderson@linaro.org>
Commit: 42221a64da3ade66b01952a84307acc7061c1a05
https://github.com/qemu/qemu/commit/42221a64da3ade66b01952a84307acc7061c1a05
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Split out tcg_out_setcond_int
Return the temp and a set of flags, to be used as a
primitive for setcond, brcond, movcond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-2-richard.henderson@linaro.org>
Commit: 2cff741da81416ba7d4d8f2470e75d0e13bccae4
https://github.com/qemu/qemu/commit/2cff741da81416ba7d4d8f2470e75d0e13bccae4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
Log Message:
-----------
tcg/mips: Always implement movcond
Expand as branch over move if not supported in the ISA.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-3-richard.henderson@linaro.org>
Commit: 3871be753f3351c21c8e384432f7798c3eed9de9
https://github.com/qemu/qemu/commit/3871be753f3351c21c8e384432f7798c3eed9de9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}
The movcond opcode is now mandatory for backends to implement.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-4-richard.henderson@linaro.org>
Commit: e0448a8b71624c97af0422df085c66d147104061
https://github.com/qemu/qemu/commit/e0448a8b71624c97af0422df085c66d147104061
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
Log Message:
-----------
tcg/mips: Implement neg opcodes
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-5-richard.henderson@linaro.org>
Commit: 0fbee2b76441db5452cde98148f600aba907f4f7
https://github.com/qemu/qemu/commit/0fbee2b76441db5452cde98148f600aba907f4f7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
Log Message:
-----------
tcg/loongarch64: Implement neg opcodes
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-6-richard.henderson@linaro.org>
Commit: b701f195d3ed39429fab5787df7c6b1c9377ab94
https://github.com/qemu/qemu/commit/b701f195d3ed39429fab5787df7c6b1c9377ab94
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/optimize.c
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
The movcond opcode is now mandatory for backends to implement.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
Commit: 9628d008bd2461e654ca47b7576002bd501d7a7d
https://github.com/qemu/qemu/commit/9628d008bd2461e654ca47b7576002bd501d7a7d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Don't free vector results
Avoid reusing vector temporaries so that we may re-use them
when propagating stores to loads.
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 986cac1d2a773f6b2d8f1051504a8af512688cbd
https://github.com/qemu/qemu/commit/986cac1d2a773f6b2d8f1051504a8af512688cbd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Pipe OptContext into reset_ts
Will be needed in the next patch.
Reviewed-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9f75e52828a967e6c95eb73e726ef1eff4c05496
https://github.com/qemu/qemu/commit/9f75e52828a967e6c95eb73e726ef1eff4c05496
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Split out cmp_better_copy
Compare two temps for "better", split out from finding
the best from a whole list. Use TCGKind, which already
gives the proper priority.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ab84dc398b3b702b0c692538b947ef65dbbdf52f
https://github.com/qemu/qemu/commit/ab84dc398b3b702b0c692538b947ef65dbbdf52f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Optimize env memory operations
Propagate stores to loads, loads to loads.
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3eaadaeb4ee9cc6a1267882b3e31c893cd99bb9e
https://github.com/qemu/qemu/commit/3eaadaeb4ee9cc6a1267882b3e31c893cd99bb9e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg: Eliminate duplicate env store operations
Notice when a constant is stored to the same location twice.
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 26aac97c849f28e23bc818035bac38be34e62983
https://github.com/qemu/qemu/commit/26aac97c849f28e23bc818035bac38be34e62983
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Split out arg_new_constant
Fixes a bug wherein raw uses of tcg_constant_internal
do not have their TempOptInfo initialized.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1551004eeb4436a163472c3b5b108a60766e74cb
https://github.com/qemu/qemu/commit/1551004eeb4436a163472c3b5b108a60766e74cb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Canonicalize subi to addi during opcode generation
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231026013945.1152174-2-richard.henderson@linaro.org>
Commit: 6334a968eec3f2498a992a7b96c1bfcaf100066f
https://github.com/qemu/qemu/commit/6334a968eec3f2498a992a7b96c1bfcaf100066f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Canonicalize subi to addi during optimization
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231026013945.1152174-3-richard.henderson@linaro.org>
Commit: f245757701ccd2d4f1c9ee0ed349e3a1d8049996
https://github.com/qemu/qemu/commit/f245757701ccd2d4f1c9ee0ed349e3a1d8049996
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Canonicalize sub2 with constants to add2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231026013945.1152174-4-richard.henderson@linaro.org>
Commit: d36ce28be424385fc9f7273bf5c15ce815b5cf4e
https://github.com/qemu/qemu/commit/d36ce28be424385fc9f7273bf5c15ce815b5cf4e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-06 (Mon, 06 Nov 2023)
Changed paths:
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Implement tcg_out_extrl_i64_i32
Build fix for missing symbol.
Cc: qemu-stable@nongnu.org
Fixes: dad2f2f5af ("tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 12b12a14c73ee200c7cff42aab6113a0649fa132
https://github.com/qemu/qemu/commit/12b12a14c73ee200c7cff42aab6113a0649fa132
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: rename ext_ifencei to ext_zifencei
Add a leading 'z' to improve grepping. When one wants to search for uses
of zifencei they're more likely to do 'grep -i zifencei' than 'grep -i
ifencei'.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231012164604.398496-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 960b389b7d15f2ebb2b4d75d98d5ffec2c6a8348
https://github.com/qemu/qemu/commit/960b389b7d15f2ebb2b4d75d98d5ffec2c6a8348
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/riscv/boot.c
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: rename ext_icsr to ext_zicsr
Add a leading 'z' to improve grepping. When one wants to search for uses
of zicsr they're more likely to do 'grep -i zicsr' than 'grep -i icsr'.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231012164604.398496-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a326a2b0b2afae9285126cb1c56e71926d3702c7
https://github.com/qemu/qemu/commit/a326a2b0b2afae9285126cb1c56e71926d3702c7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/riscv/virt.c
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/insn_trans/trans_rvzicbo.c.inc
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv: rename ext_icbom to ext_zicbom
Add a leading 'z' to improve grepping. When one wants to search for uses
of zicbom they're more likely to do 'grep -i zicbom' than 'grep -i
icbom'.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231012164604.398496-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e57039ddab55bb0f711b3bf46d39f887663243a0
https://github.com/qemu/qemu/commit/e57039ddab55bb0f711b3bf46d39f887663243a0
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/riscv/virt.c
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/insn_trans/trans_rvzicbo.c.inc
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv: rename ext_icboz to ext_zicboz
Add a leading 'z' to improve grepping. When one wants to search for uses
of zicboz they're more likely to do 'grep -i zicboz' than 'grep -i
icboz'.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231012164604.398496-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a7b69170254b15b5a40b318ed5559084ccfc466b
https://github.com/qemu/qemu/commit/a7b69170254b15b5a40b318ed5559084ccfc466b
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Without H-mode mask all HS mode inturrupts in mie.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-2-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d17bcae5f7e9f949052a1f126a7f23e7279b6d96
https://github.com/qemu/qemu/commit/d17bcae5f7e9f949052a1f126a7f23e7279b6d96
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
async flag check is performed before invoking semihosting logic.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-3-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b901c7eb701a8f4d512be3a70958150fc5d0cd90
https://github.com/qemu/qemu/commit/b901c7eb701a8f4d512be3a70958150fc5d0cd90
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
With H-Ext supported, VS bits are all hardwired to one in MIDELEG
denoting always delegated interrupts. This is being done in rmw_mideleg
but given mideleg is used in other places when routing interrupts
this change initializes it in riscv_cpu_realize to be on the safe side.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-4-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1ebad505f3d5108513bf150b901344caceb3a7c1
https://github.com/qemu/qemu/commit/1ebad505f3d5108513bf150b901344caceb3a7c1
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Split interrupt logic from riscv_cpu_update_mip.
This is to allow virtual interrupts to be inserted into S and VS
modes. Given virtual interrupts will be maintained in separate
mvip and hvip CSRs, riscv_cpu_update_mip will no longer be in the
path and interrupts need to be triggered for these cases from
rmw_hvip64 and rmw_mvip64 functions.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-5-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1697837ed98cf56a6f65edd06128151f83b99403
https://github.com/qemu/qemu/commit/1697837ed98cf56a6f65edd06128151f83b99403
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from M-mode
into S-mode using mvien and mvip csrs. IRQ filtering is a use case of
this change, i-e M-mode can stop delegating an interrupt to S-mode and
instead enable it in MIE and receive those interrupts in M-mode and then
selectively inject the interrupt using mvien and mvip.
Also, the spec doesn't mandate the interrupt to be actually supported
in hardware. Which allows M-mode to assert virtual interrupts to S-mode
that have no connection to any real interrupt events.
This is defined as part of the AIA specification [0], "5.3 Interrupt
filtering and virtual interrupts for supervisor level".
[0]:
https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231016111736.28721-6-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 40336d5b1d4c6b8b8b38c77fda254457d44fe90b
https://github.com/qemu/qemu/commit/40336d5b1d4c6b8b8b38c77fda254457d44fe90b
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from HS-mode
into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering
from HS-mode.
Also, the spec doesn't mandate the interrupt to be actually supported
in hardware. Which allows HS-mode to assert virtual interrupts to VS-mode
that have no connection to any real interrupt events.
This is defined as part of the AIA specification [0], "6.3.2 Virtual
interrupts for VS level".
[0]:
https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231016111736.28721-7-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4d84cc5887c5ed9a630f5af87e56d64ee0a98c4b
https://github.com/qemu/qemu/commit/4d84cc5887c5ed9a630f5af87e56d64ee0a98c4b
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M linux-user/riscv/target_elf.h
Log Message:
-----------
linux-user/riscv: change default cpu to 'max'
Commit f57d5f8004 deprecated the 'any' CPU type but failed to change the
default CPU for linux-user. The result is that all linux-users
invocations that doesn't specify a different CPU started to show a
deprecation warning:
$ ./build/qemu-riscv64 ./foo-novect.out
qemu-riscv64: warning: The 'any' CPU is deprecated and will be removed in the
future.
Change the default CPU for RISC-V linux-user from 'any' to 'max'.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: f57d5f8004 ("target/riscv: deprecate the 'any' CPU type")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231020074501.283063-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 257cfaed47e3263ee3c379ec7a766f5050daa920
https://github.com/qemu/qemu/commit/257cfaed47e3263ee3c379ec7a766f5050daa920
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M docs/system/riscv/virt.rst
Log Message:
-----------
docs/system/riscv: update 'virt' machine core limit
The 'virt' RISC-V machine does not have a 8 core limit. The current
limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at
this moment.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231020200247.334403-2-dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 456a65546f6761aab09275ed7055d113608e3bb2
https://github.com/qemu/qemu/commit/456a65546f6761aab09275ed7055d113608e3bb2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm/kvm-cpu.c: add missing property getters()
We got along without property getters in the KVM driver because we never
needed them. But the incoming query-cpu-model-expansion API will use
property getters and setters to retrieve the CPU characteristics.
Add the missing getters for the KVM driver for both MISA and
multi-letter extension properties. We're also adding an special getter
for absent multi-letter properties that KVM doesn't implement that
always return false.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: aeb2bc5950bda70f97c6a7fcbdf1ab2b167d4fa4
https://github.com/qemu/qemu/commit/aeb2bc5950bda70f97c6a7fcbdf1ab2b167d4fa4
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M qapi/machine-target.json
M target/riscv/riscv-qmp-cmds.c
Log Message:
-----------
qapi,risc-v: add query-cpu-model-expansion
This API is used to inspect the characteristics of a given CPU model. It
also allows users to validate a CPU model with a certain configuration,
e.g. if "-cpu X,a=true,b=false" is a valid setup for a given QEMU
binary. We'll start implementing the first part. The second requires
more changes in RISC-V CPU boot flow.
The implementation is inspired by the existing ARM
query-cpu-model-expansion impl in target/arm/arm-qmp-cmds.c. We'll
create a RISCVCPU object with the required model, fetch its existing
properties, add a couple of relevant boolean options (pmp and mmu) and
display it to users.
Here's an usage example:
./build/qemu-system-riscv64 -S -M virt -display none \
-qmp tcp:localhost:1234,server,wait=off
./scripts/qmp/qmp-shell localhost:1234
Welcome to the QMP low-level shell!
Connected to QEMU 8.1.50
(QEMU) query-cpu-model-expansion type=full model={"name":"rv64"}
{"return": {"model": {"name": "rv64", "props": {"zicond": false, "x-zvfh":
false, "mmu": true, "x-zvfbfwma": false, "x-zvfbfmin": false, "xtheadbs":
false, "xtheadbb": false, "xtheadba": false, "xtheadmemidx": false,
"smstateen": false, "zfinx": false, "Zve64f": false, "Zve32f": false,
"x-zvfhmin": false, "xventanacondops": false, "xtheadcondmov": false, "svpbmt":
false, "zbs": true, "zbc": true, "zbb": true, "zba": true, "zicboz": true,
"xtheadmac": false, "Zfh": false, "Zfa": true, "zbkx": false, "zbkc": false,
"zbkb": false, "Zve64d": false, "x-zfbfmin": false, "zk": false, "x-epmp":
false, "xtheadmempair": false, "zkt": false, "zks": false, "zkr": false, "zkn":
false, "Zfhmin": false, "zksh": false, "zknh": false, "zkne": false, "zknd":
false, "zhinx": false, "Zicsr": true, "sscofpmf": false, "Zihintntl": true,
"sstc": true, "xtheadcmo": false, "x-zvbb": false, "zksed": false, "x-zvkned":
false, "xtheadsync": false, "x-zvkg": false, "zhinxmin": false, "svadu": true,
"xtheadfmv": false, "x-zvksed": false, "svnapot": false, "pmp": true,
"x-zvknhb": false, "x-zvknha": false, "xtheadfmemidx": false, "x-zvksh": false,
"zdinx": false, "zicbom": true, "Zihintpause": true, "svinval": false, "zcf":
false, "zce": false, "zcd": false, "zcb": false, "zca": false, "x-ssaia":
false, "x-smaia": false, "zmmul": false, "x-zvbc": false, "Zifencei": true,
"zcmt": false, "zcmp": false, "Zawrs": true}}}}
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a13a6082c7488d4393453d383676ae423b38b4d8
https://github.com/qemu/qemu/commit/a13a6082c7488d4393453d383676ae423b38b4d8
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
M target/riscv/tcg/tcg-cpu.h
Log Message:
-----------
target/riscv/tcg: add tcg_cpu_finalize_features()
The query-cpu-model-expansion API is capable of passing extra properties
to a given CPU model and tell callers if this custom configuration is
valid.
The RISC-V version of the API is not quite there yet. The reason is the
realize() flow in the TCG driver, where most of the validation is done
in tcg_cpu_realizefn(). riscv_cpu_finalize_features() is then used to
validate satp_mode for both TCG and KVM CPUs.
Our ARM friends uses a concept of 'finalize_features()', a step done in
the end of realize() where the CPU features are validated. We have a
riscv_cpu_finalize_features() helper that, at this moment, is only
validating satp_mode.
Re-use this existing helper to do all CPU extension validation we
required after at the end of realize(). Make it public to allow APIs to
use it. At this moment only the TCG driver requires a realize() time
validation, thus, to avoid adding accelerator specific helpers in the
API, riscv_cpu_finalize_features() uses
riscv_tcg_cpu_finalize_features() if we are running TCG. The API will
then use riscv_cpu_finalize_features() regardless of the current
accelerator.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1df4f540d6352131cefa7ca48b637ccb774ce9e0
https://github.com/qemu/qemu/commit/1df4f540d6352131cefa7ca48b637ccb774ce9e0
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/riscv-qmp-cmds.c
Log Message:
-----------
target/riscv: handle custom props in qmp_query_cpu_model_expansion
Callers can add 'props' when querying for a cpu model expansion to see
if a given CPU model supports a certain criteria, and what's the
resulting CPU object.
If we have 'props' to handle, gather it in a QDict and use the new
riscv_cpuobj_validate_qdict_in() helper to validate it. This helper will
add the custom properties in the CPU object and validate it using
riscv_cpu_finalize_features(). Users will be aware of validation errors
if any occur, if not a CPU object with 'props' will be returned.
Here's an example with the veyron-v1 vendor CPU. Disabling vendor CPU
extensions is allowed, assuming the final config is valid. Disabling
'smstateen' is a valid expansion:
(QEMU) query-cpu-model-expansion type=full
model={"name":"veyron-v1","props":{"smstateen":false}}
{"return": {"model": {"name": "veyron-v1", "props": {"zicond": false, ...,
"smstateen": false, ...}
But enabling extensions isn't allowed for vendor CPUs. E.g. enabling 'V'
for the veyron-v1 CPU isn't allowed:
(QEMU) query-cpu-model-expansion type=full
model={"name":"veyron-v1","props":{"v":true}}
{"error": {"class": "GenericError", "desc": "'veyron-v1' CPU does not allow
enabling extensions"}}
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ef58fad0fdc7aba2c2196f9c35a89889286ef92b
https://github.com/qemu/qemu/commit/ef58fad0fdc7aba2c2196f9c35a89889286ef92b
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
M target/riscv/tcg/tcg-cpu.h
Log Message:
-----------
target/riscv: add riscv_cpu_accelerator_compatible()
Add an API to check if a given CPU is compatible with the current
accelerator.
This will allow query-cpu-model-expansion to work properly in conditions
where QEMU supports both accelerators (TCG and KVM), QEMU is then
launched using TCG, and the API requests information about a KVM only
CPU (e.g. 'host' CPU).
KVM doesn't have such restrictions and, at least in theory, all CPUs
models should work with KVM. We will revisit this API in case we decide
to restrict the amount of KVM CPUs we support.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a3abecbef0ad5e121c0d3f8f26568ab0466d9a6a
https://github.com/qemu/qemu/commit/a3abecbef0ad5e121c0d3f8f26568ab0466d9a6a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/riscv-qmp-cmds.c
Log Message:
-----------
target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion
Use the recently added riscv_cpu_accelerator_compatible() to filter
unavailable CPUs for a given accelerator. At this moment this is the
case for a QEMU built with KVM and TCG support querying a binary running
with TCG:
qemu-system-riscv64 -S -M virt,accel=tcg -display none
-qmp tcp:localhost:1234,server,wait=off
./qemu/scripts/qmp/qmp-shell localhost:1234
(QEMU) query-cpu-model-expansion type=full model={"name":"host"}
{"error": {"class": "GenericError", "desc": "'host' CPU not available with
tcg"}}
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 095fe72a128b34d4f9317c2798c6fa7762a9e3e6
https://github.com/qemu/qemu/commit/095fe72a128b34d4f9317c2798c6fa7762a9e3e6
Author: Himanshu Chauhan <hchauhan@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/csr.c
M target/riscv/pmp.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
Add epmp to extensions list and rename it to smepmp
Smepmp is a ratified extension which qemu refers to as epmp.
Rename epmp to smepmp and add it to extension list so that
it is added to the isa string.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231019065546.1431579-1-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4bf501dc0118a28699e28c01acb34e28ddeb0acc
https://github.com/qemu/qemu/commit/4bf501dc0118a28699e28c01acb34e28ddeb0acc
Author: Mayuresh Chitale <mchitale@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/pmp.c
M target/riscv/pmp.h
Log Message:
-----------
target/riscv: pmp: Clear pmp/smepmp bits on reset
As per the Priv and Smepmp specifications, certain bits such as the 'L'
bit of pmp entries and mseccfg.MML can only be cleared upon reset and it
is necessary to do so to allow 'M' mode firmware to correctly reinitialize
the pmp/smpemp state across reboots. As required by the spec, also clear
the 'A' field of pmp entries.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231019065644.1431798-1-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ac66f2f0d12d7ebb69bb45d5eb7f73fb0542bae5
https://github.com/qemu/qemu/commit/ac66f2f0d12d7ebb69bb45d5eb7f73fb0542bae5
Author: Mayuresh Chitale <mchitale@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: pmp: Ignore writes when RW=01
As per the Priv spec: "The R, W, and X fields form a collective WARL
field for which the combinations with R=0 and W=1 are reserved."
However currently such writes are not ignored as ought to be. The
combinations with RW=01 are allowed only when the Smepmp extension
is enabled and mseccfg.MML is set.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231019065705.1431868-1-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c004099330c2bb9c94984ac917815572fcd55bd0
https://github.com/qemu/qemu/commit/c004099330c2bb9c94984ac917815572fcd55bd0
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/csr.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: add zicntr extension flag for TCG
zicntr is the Base Counters and Timers extension described in chapter 12
of the unprivileged spec. It describes support for RDCYCLE, RDTIME and
RDINSTRET.
QEMU already implements it in TCG way before it was a discrete
extension. zicntr is part of the RVA22 profile, so let's add it to QEMU
to make the future profile implementation flag complete. Given than it
represents an already existing feature, default it to 'true' for all
CPUs.
For TCG, we need a way to disable zicntr if the user wants to. This is
done by restricting access to the CYCLE, TIME, and INSTRET counters via
the 'ctr()' predicate when we're about to access them.
Disabling zicntr happens via the command line or if its dependency,
zicsr, happens to be disabled. We'll check for zicsr during realize()
and, in case it's absent, disable zicntr. However, if the user was
explicit about having zicntr support, error out instead of disabling it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231023153927.435083-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b31dee8a7d3e515b5129f8ec57fb38cc193fac6e
https://github.com/qemu/qemu/commit/b31dee8a7d3e515b5129f8ec57fb38cc193fac6e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: add zicntr reg
Add zicntr support in the KVM driver now that QEMU supports it.
This reg was added in Linux 6.6.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231023153927.435083-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 082412166044a96c69c174e262f282cc6d73f019
https://github.com/qemu/qemu/commit/082412166044a96c69c174e262f282cc6d73f019
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: add zihpm extension flag for TCG
zihpm is the Hardware Performance Counters extension described in
chapter 12 of the unprivileged spec. It describes support for 29
unprivileged performance counters, hpmcounter3-hpmcounter31.
As with zicntr, QEMU already implements zihpm before it was even an
extension. zihpm is also part of the RVA22 profile, so add it to QEMU
to complement the future profile implementation. Default it to 'true'
for all existing CPUs since it was always present in the code.
As for disabling it, there is already code in place in
target/riscv/csr.c in all predicates for these counters (ctr() and
mctr()) that disables them if cpu->cfg.pmu_num is zero. Thus, setting
cpu->cfg.pmu_num to zero if 'zihpm=false' is enough to disable the
extension.
Set cpu->pmu_avail_ctrs mask to zero as well since this is also checked
to verify if the counters exist.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231023153927.435083-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b4ceb3f2f37bffab379c8aa531730d6ec31b9930
https://github.com/qemu/qemu/commit/b4ceb3f2f37bffab379c8aa531730d6ec31b9930
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: add zihpm reg
Add zihpm support in the KVM driver now that QEMU supports it.
This reg was added in Linux 6.6.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231023153927.435083-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 672ec6061f13af21cbfa560ab2c0eea1a600d950
https://github.com/qemu/qemu/commit/672ec6061f13af21cbfa560ab2c0eea1a600d950
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot
These regs were added in Linux 6.6.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231031205150.208405-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2f32dcabc2f0dfe7ee8c604dafb8ef450d78f452
https://github.com/qemu/qemu/commit/2f32dcabc2f0dfe7ee8c604dafb8ef450d78f452
Author: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: correct csr_ops[CSR_MSECCFG]
The CSR register mseccfg is used by multiple extensions: Smepm and Zkr.
Consider this when checking the existence of the register.
Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231030102105.19501-1-heinrich.schuchardt@canonical.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c0ce1f2a88c7fb7c923e1764d7af53f4cc815486
https://github.com/qemu/qemu/commit/c0ce1f2a88c7fb7c923e1764d7af53f4cc815486
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: update mail address for Weiwei Li
My Iscas mail account will be disabled soon, change to my personal
gmail account.
Signed-off-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231030081607.115118-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5ddbc83ff2f830f2e96c933d78ccf59c1507eab6
https://github.com/qemu/qemu/commit/5ddbc83ff2f830f2e96c933d78ccf59c1507eab6
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add cfg property for Zvkt extension
Vector crypto spec defines the Zvkt extension that included all of the
instructions of Zvbb & Zvbc extensions and some vector instructions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1c32b6306648ad46002a0ec13ec6719f5e9e82cb
https://github.com/qemu/qemu/commit/1c32b6306648ad46002a0ec13ec6719f5e9e82cb
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose Zvkt extension property
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 389b2e70141fda7009bcd7c2755fd84176d543b1
https://github.com/qemu/qemu/commit/389b2e70141fda7009bcd7c2755fd84176d543b1
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add cfg property for Zvkb extension
After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is
defined as a proper subset of the Zvbb extension. And both the Zvkn and
Zvks shorthand extensions replace the included Zvbb extension by Zvkb
extnesion.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-4-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1db699f8c2a4c42def5a1ad2d5b48371d28b6278
https://github.com/qemu/qemu/commit/1db699f8c2a4c42def5a1ad2d5b48371d28b6278
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvvk.c.inc
Log Message:
-----------
target/riscv: Replace Zvbb checking by Zvkb
The Zvkb extension is a proper subset of the Zvbb extension and includes
following instructions:
* vandn.[vv,vx]
* vbrev8.v
* vrev8.v
* vrol.[vv,vx]
* vror.[vv,vx,vi]
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f209cb0a83cc57bb172bff4b862932a408d46b58
https://github.com/qemu/qemu/commit/f209cb0a83cc57bb172bff4b862932a408d46b58
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose Zvkb extension property
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-6-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7cdc8ddb080863c7883762961e5012f08487ce98
https://github.com/qemu/qemu/commit/7cdc8ddb080863c7883762961e5012f08487ce98
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add cfg properties for Zvkn[c|g] extensions
Vector crypto spec defines the NIST algorithm suite related extensions
(Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-7-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 23aaefb9c9900c385c74b3490e60da2040f8200e
https://github.com/qemu/qemu/commit/23aaefb9c9900c385c74b3490e60da2040f8200e
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose Zvkn[c|g] extnesion properties
Expose the properties of NIST Algorithm Suite related extensions (Zvkn,
Zvknc, Zvkng).
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-8-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8f913d1004766c8ee96bcab78a6c39764aa5ee52
https://github.com/qemu/qemu/commit/8f913d1004766c8ee96bcab78a6c39764aa5ee52
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add cfg properties for Zvks[c|g] extensions
Vector crypto spec defines the ShangMi algorithm suite related
extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto
extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-9-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b43419f2dc5a95f6861156ecff5654ad48fec010
https://github.com/qemu/qemu/commit/b43419f2dc5a95f6861156ecff5654ad48fec010
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose Zvks[c|g] extnesion properties
Expose the properties of ShangMi Algorithm Suite related extensions
(Zvks, Zvksc, Zvksg).
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-10-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ea61ef7097d05b55cc0ff3e8826eea7fbbe0c0a9
https://github.com/qemu/qemu/commit/ea61ef7097d05b55cc0ff3e8826eea7fbbe0c0a9
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Move vector crypto extensions to riscv_cpu_extensions
Because the vector crypto specification is ratified, so move theses
extensions from riscv_cpu_experimental_exts to riscv_cpu_extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231026151828.754279-11-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ea363626ff65b2b8e6c590812f89546d5779612f
https://github.com/qemu/qemu/commit/ea363626ff65b2b8e6c590812f89546d5779612f
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M disas/riscv.h
Log Message:
-----------
disas/riscv: Add rv_fmt_vd_vs2_uimm format
Add rv_fmt_vd_vs2_uimm format for vector crypto instructions.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-12-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 434c609bef445e0dd13d514c5b12f8e47a73cd1d
https://github.com/qemu/qemu/commit/434c609bef445e0dd13d514c5b12f8e47a73cd1d
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M disas/riscv.c
M disas/riscv.h
Log Message:
-----------
disas/riscv: Add rv_codec_vror_vi for vror.vi
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-13-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9d92f56d4a44a14ec099e9af5148c4c9c85fd59e
https://github.com/qemu/qemu/commit/9d92f56d4a44a14ec099e9af5148c4c9c85fd59e
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Add support for vector crypto extensions
This patch adds following v1.0.0 ratified vector crypto extensions
support to the RISC-V disassembler.
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknha
- Zvknhb
- Zvksed
- Zvksh
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20231026151828.754279-14-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 251385fd4480c0715f3d2c76a3c76534a42570fc
https://github.com/qemu/qemu/commit/251385fd4480c0715f3d2c76a3c76534a42570fc
Author: Max Chou <max.chou@sifive.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Replace TABs with space
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-15-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d53ead72066b1502bc3989dd11f1565d472e431d
https://github.com/qemu/qemu/commit/d53ead72066b1502bc3989dd11f1565d472e431d
Author: Alistair Francis <alistair23@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/ssi/ibex_spi_host.c
Log Message:
-----------
hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
We currently don't clear the interrupts if they are disabled. This means
that if an interrupt occurs and the guest disables interrupts the QEMU
IRQ will remain high.
This doesn't immediately affect guests, but if the
guest re-enables interrupts it's possible that we will miss an
interrupt as it always remains set.
Let's update the logic to always call qemu_set_irq() even if the
interrupts are disabled to ensure we set the level low. The level will
never be high unless interrupts are enabled, so we won't generate
interrupts when we shouldn't.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231102003424.2003428-2-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c541b07de79daa293e9ccc07f3c98f575ad09f2a
https://github.com/qemu/qemu/commit/c541b07de79daa293e9ccc07f3c98f575ad09f2a
Author: Alistair Francis <alistair23@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: cpu: Set the OpenTitan priv to 1.12.0
Set the Ibex CPU priv to 1.12.0 to ensure that smepmp/epmp is correctly
enabled.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231102003424.2003428-3-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 755b41d09f516109f5ddc49aae86358c72e656d5
https://github.com/qemu/qemu/commit/755b41d09f516109f5ddc49aae86358c72e656d5
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/pmu.c
M target/riscv/pmu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Propagate error from PMU setup
More closely follow the QEMU style by returning an Error and propagating
it there is an error relating to the PMU setup.
Further simplify the function by removing the num_counters parameter as
this is available from the passed in cpu pointer.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20231031154000.18134-2-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7c1bb1d8d412f03ec7d6042971892bd0dff222b7
https://github.com/qemu/qemu/commit/7c1bb1d8d412f03ec7d6042971892bd0dff222b7
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Don't assume PMU counters are continuous
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20231031154000.18134-3-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2571a6427c4ded57e44d4c6cf92376d869a75a5c
https://github.com/qemu/qemu/commit/2571a6427c4ded57e44d4c6cf92376d869a75a5c
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/riscv/virt.c
M target/riscv/pmu.c
M target/riscv/pmu.h
Log Message:
-----------
target/riscv: Use existing PMU counter mask in FDT generation
During the FDT generation use the existing mask containing the enabled
counters rather then generating a new one. Using the existing mask will
support the use of discontinuous counters.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20231031154000.18134-4-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 69b3849bff4bd5ab82241ad09426cd9ff7078449
https://github.com/qemu/qemu/commit/69b3849bff4bd5ab82241ad09426cd9ff7078449
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/machine.c
M target/riscv/pmu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add "pmu-mask" property to replace "pmu-num"
Using a mask instead of the number of PMU devices supports the accurate
emulation of platforms that have a discontinuous set of PMU counters.
The "pmu-num" property now generates a warning when used by the user on
the command line.
Rather than storing the value for "pmu-num" convert it directly to the
mask if it is specified (overwriting the default "pmu-mask" value)
likewise the value is calculated from the mask if the property value is
obtained.
In the unusual situation that both "pmu-mask" and "pmu-num" are provided
then then the order on the command line determines which takes
precedence (later overwriting earlier.)
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231031154000.18134-5-rbradford@rivosinc.com>
[Changes by AF
- Fixup ext_zihpm logic after rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bc5e8445342fee35b35f2ed9a9f2249e060b8776
https://github.com/qemu/qemu/commit/bc5e8445342fee35b35f2ed9a9f2249e060b8776
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M docs/about/deprecated.rst
Log Message:
-----------
docs/about/deprecated: Document RISC-V "pmu-num" deprecation
This has been replaced by a "pmu-mask" property that provides much more
flexibility.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20231031154000.18134-6-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 74949263a54a1382309afba952683255c1c22ef7
https://github.com/qemu/qemu/commit/74949263a54a1382309afba952683255c1c22ef7
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/internal-common.h
M accel/tcg/ldst_atomicity.c.inc
M accel/tcg/monitor.c
M accel/tcg/translate-all.c
A host/include/loongarch64/host/atomic128-ldst.h
A host/include/loongarch64/host/cpuinfo.h
A host/include/loongarch64/host/load-extract-al16-al8.h
A host/include/loongarch64/host/store-insert-al16.h
M include/exec/cputlb.h
M include/tcg/tcg-op-common.h
M include/tcg/tcg-opc.h
M include/tcg/tcg-temp-internal.h
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/optimize.c
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.c.inc
M tcg/sparc64/tcg-target.h
M tcg/tcg-internal.h
M tcg/tcg-op-gvec.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.h
A util/cpuinfo-loongarch.c
M util/meson.build
Log Message:
-----------
Merge tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu into staging
util: Add cpuinfo for loongarch64
tcg/loongarch64: Use cpuinfo.h
tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128
host/include/loongarch64: Add atomic16 load and store
tcg: Move expanders out of line
tcg/mips: Always implement movcond
tcg/mips: Implement neg opcodes
tcg/loongarch64: Implement neg opcodes
tcg: Make movcond and neg required opcodes
tcg: Optimize env memory operations
tcg: Canonicalize sub of immediate to add
tcg/sparc64: Implement tcg_out_extrl_i64_i32
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# gpg: Signature made Tue 07 Nov 2023 10:47:25 HKT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu: (35 commits)
tcg/sparc64: Implement tcg_out_extrl_i64_i32
tcg/optimize: Canonicalize sub2 with constants to add2
tcg/optimize: Canonicalize subi to addi during optimization
tcg: Canonicalize subi to addi during opcode generation
tcg/optimize: Split out arg_new_constant
tcg: Eliminate duplicate env store operations
tcg/optimize: Optimize env memory operations
tcg/optimize: Split out cmp_better_copy
tcg/optimize: Pipe OptContext into reset_ts
tcg: Don't free vector results
tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
tcg/loongarch64: Implement neg opcodes
tcg/mips: Implement neg opcodes
tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}
tcg/mips: Always implement movcond
tcg/mips: Split out tcg_out_setcond_int
tcg: Move tcg_temp_free_* out of line
tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line
tcg: Move tcg_constant_* out of line
tcg: Unexport tcg_gen_op*_{i32,i64}
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 8aba939e77daca10eac99d9d467f65ba7df5ab3e
https://github.com/qemu/qemu/commit/8aba939e77daca10eac99d9d467f65ba7df5ab3e
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M disas/riscv.c
M disas/riscv.h
M docs/about/deprecated.rst
M docs/system/riscv/virt.rst
M hw/riscv/boot.c
M hw/riscv/virt.c
M hw/ssi/ibex_spi_host.c
M linux-user/riscv/target_elf.h
M qapi/machine-target.json
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/insn_trans/trans_rvzicbo.c.inc
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/pmp.c
M target/riscv/pmp.h
M target/riscv/pmu.c
M target/riscv/pmu.h
M target/riscv/riscv-qmp-cmds.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/tcg/tcg-cpu.h
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20231107' of
https://github.com/alistair23/qemu into staging
Third RISC-V PR for 8.2
* Rename ext_icboz to ext_zicboz
* Rename ext_icbom to ext_zicbom
* Rename ext_icsr to ext_zicsr
* Rename ext_ifencei to ext_zifencei
* Add RISC-V Virtual IRQs and IRQ filtering support
* Change default linux-user cpu to 'max'
* Update 'virt' machine core limit
* Add query-cpu-model-expansion API
* Rename epmp to smepmp and expose the extension
* Clear pmp/smepmp bits on reset
* Ignore pmp writes when RW=01
* Support zicntr/zihpm flags and disable support
* Correct CSR_MSECCFG operations
* Update mail address for Weiwei Li
* Update RISC-V vector crypto to ratified v1.0.0
* Clear the Ibex/OpenTitan SPI interrupts even if disabled
* Set the OpenTitan priv to 1.12.0
* Support discontinuous PMU counters
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# gpg: Signature made Tue 07 Nov 2023 10:28:49 HKT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20231107' of https://github.com/alistair23/qemu: (49
commits)
docs/about/deprecated: Document RISC-V "pmu-num" deprecation
target/riscv: Add "pmu-mask" property to replace "pmu-num"
target/riscv: Use existing PMU counter mask in FDT generation
target/riscv: Don't assume PMU counters are continuous
target/riscv: Propagate error from PMU setup
target/riscv: cpu: Set the OpenTitan priv to 1.12.0
hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
disas/riscv: Replace TABs with space
disas/riscv: Add support for vector crypto extensions
disas/riscv: Add rv_codec_vror_vi for vror.vi
disas/riscv: Add rv_fmt_vd_vs2_uimm format
target/riscv: Move vector crypto extensions to riscv_cpu_extensions
target/riscv: Expose Zvks[c|g] extnesion properties
target/riscv: Add cfg properties for Zvks[c|g] extensions
target/riscv: Expose Zvkn[c|g] extnesion properties
target/riscv: Add cfg properties for Zvkn[c|g] extensions
target/riscv: Expose Zvkb extension property
target/riscv: Replace Zvbb checking by Zvkb
target/riscv: Add cfg property for Zvkb extension
target/riscv: Expose Zvkt extension property
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/80aaef96b193...8aba939e77da
- [Qemu-commits] [qemu/qemu] 24a4d5: accel/tcg: Move HMP info jit and info opcount code,
Alex Bennée <=