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[Qemu-commits] [qemu/qemu] 881d10: target/hppa: Mask reserved PSW bits i
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] 881d10: target/hppa: Mask reserved PSW bits in expand_sm_imm |
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Date: |
Tue, 14 Nov 2023 09:31:39 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 881d1073d0f83d9a07e5ea3ff444e1bef9679a7c
https://github.com/qemu/qemu/commit/881d1073d0f83d9a07e5ea3ff444e1bef9679a7c
Author: Helge Deller <deller@gmx.de>
Date: 2023-11-12 (Sun, 12 Nov 2023)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Mask reserved PSW bits in expand_sm_imm
The system mask is a restricted subset of the psw, with only
a couple of reserved bits. It is better to handle this up
front in the translator than require helper_swap_system_mask
to use cpu_hppa_get_psw and cpu_hppa_put_psw.
Signed-off-by: Helge Deller <deller@gmx.de>
[rth: Handle this in expand_sm_imm not helper_swap_system_mask.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fe73674af1e80ad7375e627563042395a1a746b6
https://github.com/qemu/qemu/commit/fe73674af1e80ad7375e627563042395a1a746b6
Author: Cédric Le Goater <clg@redhat.com>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M hw/net/igb.c
M hw/net/igb_common.h
M hw/net/igb_core.c
M hw/net/igb_core.h
M hw/net/igbvf.c
M hw/net/trace-events
Log Message:
-----------
igb: Add a VF reset handler
Export the igb_vf_reset() helper routine from the PF model to let the
IGBVF model implement its own device reset.
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: d90014fc337ab77f37285b1a30fd4f545056be0a
https://github.com/qemu/qemu/commit/d90014fc337ab77f37285b1a30fd4f545056be0a
Author: Cédric Le Goater <clg@redhat.com>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M hw/core/machine.c
M hw/net/igb.c
M hw/net/igbvf.c
Log Message:
-----------
igb: Add Function Level Reset to PF and VF
The Intel 82576EB GbE Controller say that the Physical and Virtual
Functions support Function Level Reset. Add the capability to the PF
device model using device property "x-pcie-flr-init" which is "on" by
default and "off" for machines <= 8.1 to preserve compatibility.
The FLR capability of the VF model is defined according to the FLR
property of the PF, this to avoid adding an extra compatibility
property.
Cc: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Fixes: 3a977deebe6b ("Intrdocue igb device emulation")
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 1d675e59ea194fc918fe0f553eb79209b3fb3a8f
https://github.com/qemu/qemu/commit/1d675e59ea194fc918fe0f553eb79209b3fb3a8f
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: fix GIC maintenance IRQ registration
Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"),
GIC maintenance IRQ registration fails on arm64:
[ 0.979743] kvm [1]: Cannot register interrupt 9
That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case
where the maintenance IRQ is actually referred by its PPI index. Just
like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use
INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there
shouldn't be more similar issues.
Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20231110090557.3219206-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fc58891d0422607d172a3d6b3158798f2556aef1
https://github.com/qemu/qemu/commit/fc58891d0422607d172a3d6b3158798f2556aef1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: HVC at EL3 should go to EL3, not EL2
AArch64 permits code at EL3 to use the HVC instruction; however the
exception we take should go to EL3, not down to EL2 (see the pseudocode
AArch64.CallHypervisor()). Fix the target EL.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Message-id: 20231109151917.1925107-1-peter.maydell@linaro.org
Commit: 4d044472ab7666adf99d4daa0cc90b7502b90109
https://github.com/qemu/qemu/commit/4d044472ab7666adf99d4daa0cc90b7502b90109
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/arm/tcg/mte_helper.c
Log Message:
-----------
target/arm: Correct MTE tag checking for reverse-copy MOPS
When we are doing a FEAT_MOPS copy that must be performed backwards,
we call mte_mops_probe_rev(), passing it the address of the last byte
in the region we are probing. However, allocation_tag_mem_probe()
wants the address of the first byte to get the tag memory for.
Because we passed it (ptr, size) we could incorrectly trip the
allocation_tag_mem_probe() check for "does this access run across to
the following page", and if that following page happened not to be
valid then we would assert.
We know we will always be only dealing with a single page because the
code that calls mte_mops_probe_rev() ensures that. We could make
mte_mops_probe_rev() pass 'ptr - (size - 1)' to
allocation_tag_mem_probe(), but then we would have to adjust the
returned 'mem' pointer to get back to the tag RAM for the last byte
of the region. It's simpler to just pass in a size of 1 byte,
because we know that allocation_tag_mem_probe() in pure-probe
single-page mode doesn't care about the size.
Fixes: 69c51dc3723b ("target/arm: Implement MTE tag-checking functions for
FEAT_MOPS copies")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231110162546.2192512-1-peter.maydell@linaro.org
Commit: 52c773ce893f6321f20c80101aa4ea9489a6f701
https://github.com/qemu/qemu/commit/52c773ce893f6321f20c80101aa4ea9489a6f701
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M hw/mips/Kconfig
Log Message:
-----------
hw/mips: LOONGSON3V depends on UNIMP device
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: qemu-stable@nongnu.org
Fixes: c76b409fef ("hw/mips: Add Loongson-3 machine support")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231107140615.3034763-1-marcandre.lureau@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4c7ae73caf7e794a7bf909906e21381f5f01b369
https://github.com/qemu/qemu/commit/4c7ae73caf7e794a7bf909906e21381f5f01b369
Author: Alexandra Diupina <adiupina@astralinux.ru>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M hw/display/vmware_vga.c
Log Message:
-----------
hw/display/vmware_vga: fix probably typo
When calling trace_vmware_verify_rect_greater_than_bound() replace
"y" with "h" and y with h
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 02218aedb1 ("hw/display/vmware_vga: replace fprintf calls with trace
events")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231110174104.13280-1-adiupina@astralinux.ru>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0034d0395e4e92c722a7044d291b2bab42f705bd
https://github.com/qemu/qemu/commit/0034d0395e4e92c722a7044d291b2bab42f705bd
Author: Ani Sinha <anisinha@redhat.com>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
A tests/avocado/mem-addr-space-check.py
Log Message:
-----------
tests/avocado: add test to exercise processor address space memory bound
checks
QEMU has validations to make sure that a VM is not started with more memory
(static and hotpluggable memory) than what the guest processor can address
directly with its addressing bits. This change adds a test to make sure QEMU
fails to start with a specific error message when an attempt is made to
start a VM with more memory than what the processor can directly address.
The test also checks for passing cases when the address space of the processor
is capable of addressing all memory. Boundary cases are tested.
CC: imammedo@redhat.com
CC: David Hildenbrand <david@redhat.com>
Acked-by: David Hildenbrand <david@redhat.com>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Ani Sinha <anisinha@redhat.com>
Message-ID: <20231109045601.33349-1-anisinha@redhat.com>
Message-ID: <D5D8D419-76BA-4FB0-9BAC-4F7470A052FC@redhat.com>
[PMD: Use SPDX tag]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f6e8d1ef05a126de796ae03dd81e048e3ff48ff1
https://github.com/qemu/qemu/commit/f6e8d1ef05a126de796ae03dd81e048e3ff48ff1
Author: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/arm/tcg/cpu32.c
Log Message:
-----------
target/arm/tcg: enable PMU feature for Cortex-A8 and A9
According to the technical reference manual, the Cortex-A9
has a Perfomance Unit Monitor (PMU):
https://developer.arm.com/documentation/100511/0401/performance-monitoring-unit/about-the-performance-monitoring-unit
The Cortex-A8 does also.
We already already define the PMU registers when emulating the
Cortex-A8 and Cortex-A9, because we put them in v7_cp_reginfo[]
rather than guarding them behind ARM_FEATURE_PMU. So the only thing
that setting the feature bit changes is that the registers actually
do something.
Enable ARM_FEATURE_PMU for Cortex-A8 and Cortex-A9, to avoid
this anomaly.
(The A8 and A9 PMU predates the standardisation of ID_DFR0.PerfMon,
so the field there is 0, but the PMU is still present.)
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Message-id: 20231112165658.2335-1-n.ostrenkov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message; also enable PMU for A8]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e5d487c9724e0fc62b1afca9f8ea11fd072643a8
https://github.com/qemu/qemu/commit/e5d487c9724e0fc62b1afca9f8ea11fd072643a8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Use only low 2 immediate bits for PROBEI
During the conversion to decodetree, the 2-bit mask was lost.
Fixes: deee69a19fd ("target/hppa: Convert memory management insns")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 576fc9376d7f220a21807bd7759d297acb4b6072
https://github.com/qemu/qemu/commit/576fc9376d7f220a21807bd7759d297acb4b6072
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/hppa/op_helper.c
Log Message:
-----------
target/hppa: Use PRIV_P_TO_MMU_IDX in helper_probe
Direct privilege level to mmu_idx mapping has been
false for some time. Provide the correct value to
hppa_get_physical_address.
Fixes: fa824d99f9b ("target/hppa: Switch to use MMU indices 11-15")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e722e5a11212f3080456dea1c3cc5b231d1d3a2d
https://github.com/qemu/qemu/commit/e722e5a11212f3080456dea1c3cc5b231d1d3a2d
Author: Helge Deller <deller@gmx.de>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/hppa/int_helper.c
Log Message:
-----------
target/hppa: Fix calculation of CR_IIASQ back register
Need to use iasq_b and iaoq_b to determine back register of CR_IIASQ.
This fixes random faults when booting up Linux user space.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2a23f0f1189666fe453027eca60daf03c561bfd6
https://github.com/qemu/qemu/commit/2a23f0f1189666fe453027eca60daf03c561bfd6
Author: Helge Deller <deller@gmx.de>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/hppa/mem_helper.c
Log Message:
-----------
target/hppa: Fix possible overflow in TLB size calculation
Coverty found that the shift of TARGET_PAGE_SIZE (32-bit type) might
overflow. Fix it by casting TARGET_PAGE_SIZE to a 64-bit type before
doing the shift (CID 1523902 and CID 1523908).
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Helge Deller <deller@gmx.de>
Message-Id: <ZU6F/H8CZr3q4pP/@p100>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 17fe594c59c7a7304c663534ffb0853eb7e903d5
https://github.com/qemu/qemu/commit/17fe594c59c7a7304c663534ffb0853eb7e903d5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/hppa/cpu.h
M target/hppa/mem_helper.c
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Introduce MMU_IDX_MMU_DISABLED
Reduce the number of direct checks against MMU_PHYS_IDX.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 451d993d58fb577425f8a79cdaf4ee213a72f702
https://github.com/qemu/qemu/commit/451d993d58fb577425f8a79cdaf4ee213a72f702
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/hppa/cpu.h
M target/hppa/mem_helper.c
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX
Align the language with pa2.0, separating absolute and physical.
The translation from absolute to physical depends on PSW.W, and
we prefer not to flush between changes, therefore use 2 mmu_idx.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fa71b4f84fb88c034ece3f3928e4d3a72e49b82f
https://github.com/qemu/qemu/commit/fa71b4f84fb88c034ece3f3928e4d3a72e49b82f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M target/hppa/cpu-param.h
M target/hppa/mem_helper.c
Log Message:
-----------
target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40
This is the value that is supported by both PA-8500 and Astro.
If we support a larger address space than expected, we trip up
software that did not fill in all of the page table bits,
expecting them to be ignored.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8066102df12fecfac7b076bd6aa208e63f8f0b04
https://github.com/qemu/qemu/commit/8066102df12fecfac7b076bd6aa208e63f8f0b04
Author: Helge Deller <deller@gmx.de>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M hw/pci-host/astro.c
M hw/pci-host/meson.build
Log Message:
-----------
hw/pci-host/astro: Fix boot for C3700 machine
Apply the "32-bit PCI addressing on 40-bit Runway" as the default
iommu transformation. This allows PCI devices to dma PDC memory.
Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e274d2a777de168082b36a31b6b5ea2b9185e960
https://github.com/qemu/qemu/commit/e274d2a777de168082b36a31b6b5ea2b9185e960
Author: Helge Deller <deller@gmx.de>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Move software power button address to page zero
Something appears to be off between the 64-bit CPU, the 32-bit PDC
(SeaBIOS-hppa firmware), and the 64-bit kernel in addressing the
power button address in high-mapped firmware memory.
Use a 32-bit value at PAGE0->pad0[4] instead.
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ec6f3fc3ef0bc0bb8cbec0a62767a32e3f00aa74
https://github.com/qemu/qemu/commit/ec6f3fc3ef0bc0bb8cbec0a62767a32e3f00aa74
Author: Helge Deller <deller@gmx.de>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M pc-bios/hppa-firmware.img
M roms/seabios-hppa
Log Message:
-----------
target/hppa: Update to SeaBIOS-hppa from version 10 to 12
SEABIOS_HPPA_VERSION 12 contains those fixes and enhancements:
- Reduce debug level
- Update README file for PA-RISC
- Fix debug name of CPU_HPA_xx if xx >= 10
- Disable device indexing
SEABIOS_HPPA_VERSION 11 contains those fixes and enhancements
(mostly to enable support for 64-bit Linux kernel):
- Fixed 64-bit CPU detection via "mfctl,w" instruction
- Implement PDC_PSW for 64-bit CPUs
- Added PAT PDC functions:
- PDC_PAT_CELL
- PDC_PAT_CHASSIS_LOG
- PDC_PAT_PD_GET_ADDR_MAP
- PDC_PAT_CPU
- Fix return value of PDC_CACHE_RET_SPID space-id bits
- Introduce new default software IDs for the machines
- Fix CPU and FPU model numbers
- Fix 64-bit SMP rendezvous
- Fix Linux 64-bit kernel crash in STI due to usage of unsigned
32-bit "next_font" pointer in sti header files
- Fix graphics output to LASI artist card on PA2.0 machines
- More USB OHCI endianess fixes
- Fixes which make ODE run on B160L
- Fixes which make ODE detect Astro Runway port and CPUs
- Implement "firmware unlocking" via PDC_MODEL/PDC_MODEL_CAPABILITIES call
- Add subfunction 2 for PDC_MODEL_VERSIONS
Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f88131d931219bf76bb1bbf3bd8d6ca941a91ae3
https://github.com/qemu/qemu/commit/f88131d931219bf76bb1bbf3bd8d6ca941a91ae3
Author: Helge Deller <deller@gmx.de>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Require at least SeaBIOS-hppa version 12
The new SeaBIOS-hppa version 12 includes the necessary fixes to
support emulated PA2.0 CPUs and which allows starting 64-bit Linux
kernels in the guest.
To boot a 64-bit machine use the "-machine C3700" qemu option.
Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0b2af475e9f325e1db98148d5423de61da6bf110
https://github.com/qemu/qemu/commit/0b2af475e9f325e1db98148d5423de61da6bf110
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M tests/avocado/machine_s390_ccw_virtio.py
Log Message:
-----------
tests/avocado/machine_s390_ccw_virtio.py: Fix SyntaxWarnings from python 3.12
Python 3.12 now warns about backslashes in strings that aren't used
for escaping a special character from Python. Silence the warning
by using raw strings here instead.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231113140721.46903-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 04c0a003dd33c7f1dea989319085984822c768e6
https://github.com/qemu/qemu/commit/04c0a003dd33c7f1dea989319085984822c768e6
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-13 (Mon, 13 Nov 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: update virtio-fs mailing list address
The old virtio-fs mailing list address is no longer in use. Switch to
the new mailing list address.
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Vivek Goyal <vgoyal@redhat.com>
Cc: German Maglione <gmaglione@redhat.com>
Cc: Hanna Czenczek <hreitz@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: German Maglione <gmaglione@redhat.com>
Message-ID: <20231111004920.148348-1-stefanha@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 816644b1219900875f47d7adf9bfb283f1b29aa0
https://github.com/qemu/qemu/commit/816644b1219900875f47d7adf9bfb283f1b29aa0
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2023-11-14 (Tue, 14 Nov 2023)
Changed paths:
M target/s390x/arch_dump.c
Log Message:
-----------
target/s390x/dump: Remove unneeded dump info function pointer init
dump_state_prepare() now sets the function pointers to NULL so we only
need to touch them if we're going to use them.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231109120443.185979-2-frankja@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: e72629e5149aba6f44122ea6d2a803ef136a0c6b
https://github.com/qemu/qemu/commit/e72629e5149aba6f44122ea6d2a803ef136a0c6b
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2023-11-14 (Tue, 14 Nov 2023)
Changed paths:
M dump/dump.c
M include/sysemu/dump-arch.h
Log Message:
-----------
dump: Add arch cleanup function
Some architectures (s390x) need to cleanup after a failed dump to be
able to continue to run the vm. Add a cleanup function pointer and
call it if it's set.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20231109120443.185979-3-frankja@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: d12a91e0baafce7b1cbacff7cf9339eeb0011732
https://github.com/qemu/qemu/commit/d12a91e0baafce7b1cbacff7cf9339eeb0011732
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2023-11-14 (Tue, 14 Nov 2023)
Changed paths:
M target/s390x/arch_dump.c
Log Message:
-----------
target/s390x/arch_dump: Add arch cleanup function for PV dumps
PV dumps block vcpu runs until dump end is reached. If there's an
error between PV dump init and PV dump end the vm will never be able
to run again. One example of such an error is insufficient disk space
for the dump file.
Let's add a cleanup function that tries to do a dump end. The dump
completion data is discarded but there's no point in writing it to a
file anyway if there's a possibility that other PV dump data is
missing.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20231109120443.185979-4-frankja@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 315088134fe82eabbf2e91e1a7644aa3e0573c03
https://github.com/qemu/qemu/commit/315088134fe82eabbf2e91e1a7644aa3e0573c03
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-14 (Tue, 14 Nov 2023)
Changed paths:
M hw/hppa/machine.c
M hw/pci-host/astro.c
M hw/pci-host/meson.build
M pc-bios/hppa-firmware.img
M roms/seabios-hppa
M target/hppa/cpu-param.h
M target/hppa/cpu.h
M target/hppa/int_helper.c
M target/hppa/mem_helper.c
M target/hppa/op_helper.c
M target/hppa/translate.c
Log Message:
-----------
Merge tag 'pull-pa-20231113' of https://gitlab.com/rth7680/qemu into staging
target/hppa: Mask reserved PSW bits in expand_sm_imm
target/hppa: Fix calculation of CR_IIASQ back register
target/hppa: Fix possible overflow in TLB size calculation
target/hppa: Fix probe instruction
target/hppa: Split MMU_PHYS_IDX to MMU_ABS_IDX, MMU_ABS_W_IDX
target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40
hw/pci-host/astro: Translate 32-bit pci onto 40-bit runway bus
hw/hppa: Update SeaBIOS-hppa to version 12
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 13 Nov 2023 12:30:06 EST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-pa-20231113' of https://gitlab.com/rth7680/qemu:
hw/hppa: Require at least SeaBIOS-hppa version 12
target/hppa: Update to SeaBIOS-hppa from version 10 to 12
hw/hppa: Move software power button address to page zero
hw/pci-host/astro: Fix boot for C3700 machine
target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40
target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX
target/hppa: Introduce MMU_IDX_MMU_DISABLED
target/hppa: Fix possible overflow in TLB size calculation
target/hppa: Fix calculation of CR_IIASQ back register
target/hppa: Use PRIV_P_TO_MMU_IDX in helper_probe
target/hppa: Use only low 2 immediate bits for PROBEI
target/hppa: Mask reserved PSW bits in expand_sm_imm
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 3b06e4058db6e535bf9f3d29ec9ec036b060d1c2
https://github.com/qemu/qemu/commit/3b06e4058db6e535bf9f3d29ec9ec036b060d1c2
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-14 (Tue, 14 Nov 2023)
Changed paths:
M hw/arm/virt.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/translate-a64.c
Log Message:
-----------
Merge tag 'pull-target-arm-20231113' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/virt: fix GIC maintenance IRQ registration
* target/arm: HVC at EL3 should go to EL3, not EL2
* target/arm: Correct MTE tag checking for reverse-copy MOPS
* target/arm/tcg: enable PMU feature for Cortex-A8 and A9
# -----BEGIN PGP SIGNATURE-----
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# =4D8I
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 13 Nov 2023 12:45:33 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20231113' of
https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm/tcg: enable PMU feature for Cortex-A8 and A9
target/arm: Correct MTE tag checking for reverse-copy MOPS
target/arm: HVC at EL3 should go to EL3, not EL2
hw/arm/virt: fix GIC maintenance IRQ registration
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 9f7c4f60ccf7c49095969c6f7cc572dba8e6f20d
https://github.com/qemu/qemu/commit/9f7c4f60ccf7c49095969c6f7cc572dba8e6f20d
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-14 (Tue, 14 Nov 2023)
Changed paths:
M hw/display/vmware_vga.c
M hw/mips/Kconfig
M tests/avocado/machine_s390_ccw_virtio.py
A tests/avocado/mem-addr-space-check.py
Log Message:
-----------
Merge tag 'misc-fixes-20231113' of https://github.com/philmd/qemu into staging
Misc fixes for 8.2
- Missing Kconfig dependency in hw/mips (Marc-André)
- Typo in VMWare model (Alexandra)
- New avocado test for x86 processors addressing (Ani)
- Fix SyntaxWarnings in avocado (Thomas)
- Update virtio-fs mailing list address in MAINTAINERS (Stefan)
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 13 Nov 2023 13:16:44 EST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'misc-fixes-20231113' of https://github.com/philmd/qemu:
MAINTAINERS: update virtio-fs mailing list address
tests/avocado/machine_s390_ccw_virtio.py: Fix SyntaxWarnings from python 3.12
tests/avocado: add test to exercise processor address space memory bound
checks
hw/display/vmware_vga: fix probably typo
hw/mips: LOONGSON3V depends on UNIMP device
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 52105c645857c2d24bb5089f19a17ed80a3a8e96
https://github.com/qemu/qemu/commit/52105c645857c2d24bb5089f19a17ed80a3a8e96
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-14 (Tue, 14 Nov 2023)
Changed paths:
M hw/core/machine.c
M hw/net/igb.c
M hw/net/igb_common.h
M hw/net/igb_core.c
M hw/net/igb_core.h
M hw/net/igbvf.c
M hw/net/trace-events
Log Message:
-----------
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
# -----BEGIN PGP SIGNATURE-----
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# gpg: Signature made Mon 13 Nov 2023 21:39:31 EST
# gpg: using RSA key EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat)
<jasowang@redhat.com>" [full]
# Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211
* tag 'net-pull-request' of https://github.com/jasowang/qemu:
igb: Add Function Level Reset to PF and VF
igb: Add a VF reset handler
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 6d44474b3b47af21c7b01f3ad781373f1a6a2d78
https://github.com/qemu/qemu/commit/6d44474b3b47af21c7b01f3ad781373f1a6a2d78
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-14 (Tue, 14 Nov 2023)
Changed paths:
M dump/dump.c
M include/sysemu/dump-arch.h
M target/s390x/arch_dump.c
Log Message:
-----------
Merge tag 'pull-request-2023-11-14' of https://gitlab.com/thuth/qemu into
staging
* Fix s390x PV dumps in case of errors
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 14 Nov 2023 06:42:22 EST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2023-11-14' of https://gitlab.com/thuth/qemu:
target/s390x/arch_dump: Add arch cleanup function for PV dumps
dump: Add arch cleanup function
target/s390x/dump: Remove unneeded dump info function pointer init
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/f78ea7ddb0e1...6d44474b3b47