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[Qemu-commits] [qemu/qemu] 11a3c4: target/arm: Set IL bit for pauth, SVE
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] 11a3c4: target/arm: Set IL bit for pauth, SVE access, BTI ... |
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Date: |
Tue, 28 Nov 2023 15:13:20 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 11a3c4a286d5dc603582ea0a1fca62c2ec0a1aee
https://github.com/qemu/qemu/commit/11a3c4a286d5dc603582ea0a1fca62c2ec0a1aee
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M target/arm/syndrome.h
Log Message:
-----------
target/arm: Set IL bit for pauth, SVE access, BTI trap syndromes
The syndrome register value always has an IL field at bit 25, which
is 0 for a trap on a 16 bit instruction, and 1 for a trap on a 32
bit instruction (or for exceptions which aren't traps on a known
instruction, like PC alignment faults). This means that our
syn_*() functions should always either take an is_16bit argument to
determine whether to set the IL bit, or else unconditionally set it.
We missed setting the IL bit for the syndrome for three kinds of trap:
* an SVE access exception
* a pointer authentication check failure
* a BTI (branch target identification) check failure
All of these traps are AArch64 only, and so the instruction causing
the trap is always 64 bit. This means we can unconditionally set
the IL bit in the syn_*() function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231120150121.3458408-1-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8d37a1425b9954d7e445615dcad23456515e24c0
https://github.com/qemu/qemu/commit/8d37a1425b9954d7e445615dcad23456515e24c0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M target/arm/helper.c
M tests/tcg/aarch64/Makefile.softmmu-target
A tests/tcg/aarch64/system/vtimer.c
Log Message:
-----------
target/arm: Handle overflow in calculation of next timer tick
In commit edac4d8a168 back in 2015 when we added support for
the virtual timer offset CNTVOFF_EL2, we didn't correctly update
the timer-recalculation code that figures out when the timer
interrupt is next going to change state. We got it wrong in
two ways:
* for the 0->1 transition, we didn't notice that gt->cval + offset
can overflow a uint64_t
* for the 1->0 transition, we didn't notice that the transition
might now happen before the count rolls over, if offset > count
In the former case, we end up trying to set the next interrupt
for a time in the past, which results in QEMU hanging as the
timer fires continuously.
In the latter case, we would fail to update the interrupt
status when we are supposed to.
Fix the calculations in both cases.
The test case is Alex Bennée's from the bug report, and tests
the 0->1 transition overflow case.
Fixes: edac4d8a168 ("target-arm: Add CNTVOFF_EL2")
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/60
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231120173506.3729884-1-peter.maydell@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 75d0e6b5c6deb08dd6cc184adba3668055680e7b
https://github.com/qemu/qemu/commit/75d0e6b5c6deb08dd6cc184adba3668055680e7b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/net/can/xlnx-zynqmp-can.c
Log Message:
-----------
hw/net/can/xlnx-zynqmp: Avoid underflow while popping TX FIFOs
Per https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format
Message Format
The same message format is used for RXFIFO, TXFIFO, and TXHPB.
Each message includes four words (16 bytes). Software must read
and write all four words regardless of the actual number of data
bytes and valid fields in the message.
There is no mention in this reference manual about what the
hardware does when not all four words are written. To fix the
reported underflow behavior when DATA2 register is written,
I choose to fill the data with the previous content of the
ID / DLC / DATA1 registers, which is how I expect hardware
would do.
Note there is no hardware flag raised under such condition.
Reported-by: Qiang Liu <cyruscyliu@gmail.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Vikram Garhwal <vikram.garhwal@amd.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231124183325.95392-2-philmd@linaro.org
Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1425
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Vikram Garhwal <vikram.garhwal@amd.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8729856c1904c11a9b016cba600767f814e237b1
https://github.com/qemu/qemu/commit/8729856c1904c11a9b016cba600767f814e237b1
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/net/can/xlnx-zynqmp-can.c
Log Message:
-----------
hw/net/can/xlnx-zynqmp: Avoid underflow while popping RX FIFO
Per https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format
Message Format
The same message format is used for RXFIFO, TXFIFO, and TXHPB.
Each message includes four words (16 bytes). Software must read
and write all four words regardless of the actual number of data
bytes and valid fields in the message.
There is no mention in this reference manual about what the
hardware does when not all four words are read. To fix the
reported underflow behavior, I choose to fill the 4 frame data
registers when the first register (ID) is accessed, which is how
I expect hardware would do.
Reported-by: Qiang Liu <cyruscyliu@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Vikram Garhwal <vikram.garhwal@amd.com>
Message-id: 20231124183325.95392-3-philmd@linaro.org
Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1427
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Vikram Garhwal <vikram.garhwal@amd.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 837053a7f491b445088eac647abe7f462c50f59a
https://github.com/qemu/qemu/commit/837053a7f491b445088eac647abe7f462c50f59a
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/virtio/virtio-pci.c
M include/hw/virtio/virtio-pci.h
Log Message:
-----------
hw/virtio: Add VirtioPCIDeviceTypeInfo::instance_finalize field
The VirtioPCIDeviceTypeInfo structure, added in commit a4ee4c8baa
("virtio: Helper for registering virtio device types") got extended
in commit 8ea90ee690 ("virtio: add class_size") with the @class_size
field. Do similarly with the @instance_finalize field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231121174051.63038-2-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c9a4aa06dfce0fde1e279e1ea0c1945582ec0d16
https://github.com/qemu/qemu/commit/c9a4aa06dfce0fde1e279e1ea0c1945582ec0d16
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/virtio/virtio-iommu-pci.c
Log Message:
-----------
hw/virtio: Free VirtIOIOMMUPCI::vdev.reserved_regions[] on finalize()
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 8077b8e549 added:
DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI,
vdev.nb_reserved_regions, vdev.reserved_regions,
qdev_prop_reserved_region, ReservedRegion),
but forgot to free the 'vdev.reserved_regions' array. Do it in the
instance_finalize() handler.
Cc: qemu-stable@nongnu.org
Fixes: 8077b8e549 ("virtio-iommu-pci: Add array of Interval properties") #
v5.1.0+
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20231121174051.63038-3-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 896dd6ff7b9f2575f1a908a07f26a70b58d8b675
https://github.com/qemu/qemu/commit/896dd6ff7b9f2575f1a908a07f26a70b58d8b675
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/misc/mps2-scc.c
Log Message:
-----------
hw/misc/mps2-scc: Free MPS2SCC::oscclk[] array on finalize()
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 4fb013afcc added:
DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset,
qdev_prop_uint32, uint32_t),
but forgot to free the 'oscclk_reset' array. Do it in the
instance_finalize() handler.
Cc: qemu-stable@nongnu.org
Fixes: 4fb013afcc ("hw/misc/mps2-scc: Support configurable number of OSCCLK
values") # v6.0.0+
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231121174051.63038-4-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 49b3e28b7bdfe771150d05c4b5860aa7854a4232
https://github.com/qemu/qemu/commit/49b3e28b7bdfe771150d05c4b5860aa7854a4232
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/nvram/xlnx-efuse.c
Log Message:
-----------
hw/nvram/xlnx-efuse: Free XlnxEFuse::ro_bits[] array on finalize()
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 68fbcc344e added:
DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits,
qdev_prop_uint32, uint32_t),
but forgot to free the 'ro_bits' array. Do it in the instance_finalize
handler.
Cc: qemu-stable@nongnu.org
Fixes: 68fbcc344e ("hw/nvram: Introduce Xilinx eFuse QOM") # v6.2.0+
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231121174051.63038-5-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4f10c66077e39969940d928077560665e155cac8
https://github.com/qemu/qemu/commit/4f10c66077e39969940d928077560665e155cac8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/nvram/xlnx-versal-efuse-ctrl.c
Log Message:
-----------
hw/nvram/xlnx-efuse-ctrl: Free XlnxVersalEFuseCtrl[] "pg0-lock" array
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 9e4aa1fafe added:
DEFINE_PROP_ARRAY("pg0-lock",
XlnxVersalEFuseCtrl, extra_pg0_lock_n16,
extra_pg0_lock_spec, qdev_prop_uint16, uint16_t),
but forgot to free the 'extra_pg0_lock_spec' array. Do it in the
instance_finalize() handler.
Cc: qemu-stable@nongnu.org
Fixes: 9e4aa1fafe ("hw/nvram: Xilinx Versal eFuse device") # v6.2.0+
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231121174051.63038-6-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6e782ffd555808378f69dd606641f0c4b5ca6120
https://github.com/qemu/qemu/commit/6e782ffd555808378f69dd606641f0c4b5ca6120
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/input/stellaris_gamepad.c
Log Message:
-----------
hw/input/stellaris_gamepad: Free StellarisGamepad::keycodes[] array
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit a75f336b97 added:
DEFINE_PROP_ARRAY("keycodes", StellarisGamepad, num_buttons,
keycodes, qdev_prop_uint32, uint32_t),
but forgot to free the 'keycodes' array. Do it in the instance_finalize
handler.
Fixes: a75f336b97 ("hw/input/stellaris_input: Convert to qdev")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231121174051.63038-7-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 90bb6d676489b5cc063858ece263e1586795803f
https://github.com/qemu/qemu/commit/90bb6d676489b5cc063858ece263e1586795803f
Author: Frederic Konrad <fkonrad@amd.com>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/ssi/xilinx_spips.c
M include/hw/ssi/xilinx_spips.h
Log Message:
-----------
hw/ssi/xilinx_spips: fix an out of bound access
The spips, qspips, and zynqmp-qspips share the same realize function
(xilinx_spips_realize) and initialize their io memory region with different
mmio_ops passed through the class. The size of the memory region is set to
the largest area (0x200 bytes for zynqmp-qspips) thus it is possible to write
out of s->regs[addr] in xilinx_spips_write for spips and qspips.
This fixes that wrong behavior.
Reviewed-by: Luc Michel <luc.michel@amd.com>
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20231124143505.1493184-2-fkonrad@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a9bc470ec208bd27a82100abc9dccf1b69f41b45
https://github.com/qemu/qemu/commit/a9bc470ec208bd27a82100abc9dccf1b69f41b45
Author: Frederic Konrad <fkonrad@amd.com>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/dma/xlnx_csu_dma.c
M include/hw/misc/xlnx-versal-cframe-reg.h
M include/hw/misc/xlnx-versal-cfu.h
M include/hw/misc/xlnx-versal-pmc-iou-slcr.h
M include/hw/ssi/xlnx-versal-ospi.h
Log Message:
-----------
hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models
It seems that the url changed a bit, and it triggers an error. Fix the URLs so
the documentation can be reached again.
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20231124143505.1493184-3-fkonrad@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1ee80592bf24eabef77e2260a86d9358b54c08fd
https://github.com/qemu/qemu/commit/1ee80592bf24eabef77e2260a86d9358b54c08fd
Author: Frederic Konrad <fkonrad@amd.com>
Date: 2023-11-27 (Mon, 27 Nov 2023)
Changed paths:
M hw/dma/xlnx_csu_dma.c
Log Message:
-----------
hw/dma/xlnx_csu_dma: don't throw guest errors when stopping the SRC DMA
UG1087 states for the source channel that: if SIZE is programmed to 0, and the
DMA is started, the interrupts DONE and MEM_DONE will be asserted.
This implies that it is allowed for the guest to stop the source DMA by writing
a size of 0 to the SIZE register, so remove the LOG_GUEST_ERROR in that case.
While at it remove the comment marking the SIZE register as write-only.
See:
https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/CSUDMA_SRC_SIZE-CSUDMA-Register
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20231124143505.1493184-4-fkonrad@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 57c3150accefcb770dbf02539d723fb3864d49ea
https://github.com/qemu/qemu/commit/57c3150accefcb770dbf02539d723fb3864d49ea
Author: Samuel Tardieu <sam@rfc1149.net>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M target/hexagon/idef-parser/prepare
Log Message:
-----------
target/hexagon/idef-parser/prepare: use env to invoke bash
This file is the only one involved in the compilation process which
still uses the /bin/bash path.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-ID: <20231123211506.636533-1-sam@rfc1149.net>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 7e01bd80c1580aa523d2a35c433d57266b9a396a
https://github.com/qemu/qemu/commit/7e01bd80c1580aa523d2a35c433d57266b9a396a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M hw/isa/vt82c686.c
M include/hw/isa/vt82c686.h
Log Message:
-----------
hw/isa/vt82c686: Bring back via_isa_set_irq()
The VIA integrated south bridge chips combine several functions and
allow routing their interrupts to any of the ISA IRQs also allowing
multiple sources to share the same ISA IRQ. E.g. pegasos2 firmware
configures everything to use IRQ 9 but amigaone routes them to
separate ISA IRQs so the current simplified routing does not work.
Bring back via_isa_set_irq() and change it to take the component that
wants to change an IRQ and keep track of interrupt status of each
source separately and do the mapping to ISA IRQ within the ISA bridge.
This may not handle cases when an ISA IRQ is controlled by devices
directly, not going through via_isa_set_irq() such as serial, parallel
or keyboard but these IRQs being conventionally fixed are not likely
to be change by guests or share with other devices so this does not
cause a problem in practice.
This reverts commit 4e5a20b6da9b1f6d2e9621ed7eb8b239560104ae.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID:
<1c3902d4166234bef0a476026441eaac3dd6cda5.1701035944.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 032a443be6ae472d9b2cb19ed03afe302f47e47f
https://github.com/qemu/qemu/commit/032a443be6ae472d9b2cb19ed03afe302f47e47f
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M hw/usb/vt82c686-uhci-pci.c
Log Message:
-----------
hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts
This device is part of a superio/ISA bridge chip and IRQs from it are
routed to an ISA interrupt. Use via_isa_set_irq() function to implement
this in a vt82c686-uhci-pci specific irq handler.
This reverts commit 422a6e8075752bc5342afd3eace23a4990dd7d98.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID:
<ed5cdeaba7cf01eebdaa35f84c63427f4d8876b1.1701035944.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 01f13ee24578e7a1ab91bb6b2dac1c84c1902bf2
https://github.com/qemu/qemu/commit/01f13ee24578e7a1ab91bb6b2dac1c84c1902bf2
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
hw/isa/vt82c686: Route PIRQ inputs using via_isa_set_irq()
The chip has 4 pins (called PIRQA-D in VT82C686B and PINTA-D in
VT8231) that are meant to be connected to PCI IRQ lines and allow
routing PCI interrupts to the ISA PIC. Route these in
via_isa_set_irq() to make it possible to share them with internal
functions that can also be routed to the same ISA IRQs.
Fixes: 2fdadd02e675caca4aba4ae26317701fe2c4c901
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID:
<8c4513d8b78fac40e6d4e65a0a4b3a7f2f278a4b.1701035944.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0ed083a1bcdbdfe77ded69b3524ad22d120fae03
https://github.com/qemu/qemu/commit/0ed083a1bcdbdfe77ded69b3524ad22d120fae03
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M hw/audio/via-ac97.c
M hw/isa/vt82c686.c
Log Message:
-----------
hw/audio/via-ac97: Route interrupts using via_isa_set_irq()
This device is a function of VIA south bridge and should allow setting
interrupt routing within that chip. This is implemented in
via_isa_set_irq().
Fixes: eb604411a78b82c468e2b8d81a9401eb8b9c7658
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID:
<5329840e4be6dd8ae143d07cbfe61d8d2d106654.1701035944.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 235948bf53860a1e2df5134eae7b0a30a971a124
https://github.com/qemu/qemu/commit/235948bf53860a1e2df5134eae7b0a30a971a124
Author: Gihun Nam <gihun.nam@outlook.com>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M hw/avr/atmega.c
M target/avr/cpu.c
M target/avr/cpu.h
Log Message:
-----------
hw/avr/atmega: Fix wrong initial value of stack pointer
The current implementation initializes the stack pointer of AVR devices
to 0. Although older AVR devices used to be like that, newer ones set
it to RAMEND.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1525
Signed-off-by: Gihun Nam <gihun.nam@outlook.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID:
<PH0P222MB0010877445B594724D40C924DEBDA@PH0P222MB0010.NAMP222.PROD.OUTLOOK.COM>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0180a744636e6951996240b96a250d20ad0fad0d
https://github.com/qemu/qemu/commit/0180a744636e6951996240b96a250d20ad0fad0d
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M docs/devel/s390-cpu-topology.rst
Log Message:
-----------
docs/s390: Fix wrong command example in s390-cpu-topology.rst
>From s390_possible_cpu_arch_ids() in hw/s390x/s390-virtio-ccw.c, the
"core-id" is the index of possible_cpus->cpus[], so it should only be
less than possible_cpus->len, which is equal to ms->smp.max_cpus.
Fix the wrong "core-id" 112, because it isn't less than maxcpus (36) in
-smp, and the valid core ids are 0-35 inclusive.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Message-ID: <20231127134917.568552-1-zhao1.liu@linux.intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1376d1c13a44e5c41b214a678484739d221457af
https://github.com/qemu/qemu/commit/1376d1c13a44e5c41b214a678484739d221457af
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M hw/dma/xlnx_csu_dma.c
M hw/input/stellaris_gamepad.c
M hw/misc/mps2-scc.c
M hw/net/can/xlnx-zynqmp-can.c
M hw/nvram/xlnx-efuse.c
M hw/nvram/xlnx-versal-efuse-ctrl.c
M hw/ssi/xilinx_spips.c
M hw/virtio/virtio-iommu-pci.c
M hw/virtio/virtio-pci.c
M include/hw/misc/xlnx-versal-cframe-reg.h
M include/hw/misc/xlnx-versal-cfu.h
M include/hw/misc/xlnx-versal-pmc-iou-slcr.h
M include/hw/ssi/xilinx_spips.h
M include/hw/ssi/xlnx-versal-ospi.h
M include/hw/virtio/virtio-pci.h
M target/arm/helper.c
M target/arm/syndrome.h
M tests/tcg/aarch64/Makefile.softmmu-target
A tests/tcg/aarch64/system/vtimer.c
Log Message:
-----------
Merge tag 'pull-target-arm-20231127' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Set IL bit for pauth, SVE access, BTI trap syndromes
* Handle overflow in calculation of next timer tick
* hw/net/can/xlnx-zynqmp: Avoid underflow when popping FIFOs
* Various devices: Free array property memory on device finalize
* hw/ssi/xilinx_spips: fix an out of bound access
* hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models
* hw/dma/xlnx_csu_dma: don't throw guest errors when stopping the SRC DMA
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVkzLAZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3o79D/0Yh7Q7N4+fc4xdBK5hb1GN
# 31rBWZ3z0XzBzXrN80g6ig5i+CvTq7+120yx4Kl5bdyAMGdXpryTeNSoa4ewmNtC
# +c6pqV8IUIHA3axepuHtwjs4wRzWoFz13gy+X/1spfhcrtFpWyRt0f3cc1fElhzX
# 2K/4H9TD2d5yZBvaKLoJ6GzdK2wtWfucvWQDOUigRF7rvSST3awZ6gkumm+/6EM5
# vbIVOqi+0JcnWKJj0i4S1vRUPg0+CuaZN8glXcGkq2BaMfOohpjFGTMY0KsAK1Cv
# Ow1guxxy2mcLixQ8pX7ii5WHVDCuPqTVcwHUQJqN5Ln6CFEre38jM1ZwgHpWhb8G
# CoVOu2B96QwPoICD7QomaKCJYHkAczC4KETsTz/Mc+zcU6+cQiv0swc2sDhwBlmT
# weHQAmZg5dPRl3DQ/8F3llhdYyvOGnUpaaBauJiuH2I5n/qhqbvcgu9G7pGwd2gm
# lk8LuzjbVEtBu2jFlPCMpvuSuJJciR/3/QdHMGlN6L0ooY6dFL9puW51wFKSh+Kx
# JqetuUJXVWLTiL9ekLnNPQkuQQwP3WQsIvQO8tjEiuojw1utk/50JPmXg/xHEahx
# rN8aiLstR4olh1i+CrIee3QR6IwhqZmvEVHROIw0ExJ1L04FCCtPlvJ/G2gD1ta2
# oLvqWLlc752+nND72lIJZg==
# =X700
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 27 Nov 2023 12:06:56 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20231127' of
https://git.linaro.org/people/pmaydell/qemu-arm:
hw/dma/xlnx_csu_dma: don't throw guest errors when stopping the SRC DMA
hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models
hw/ssi/xilinx_spips: fix an out of bound access
hw/input/stellaris_gamepad: Free StellarisGamepad::keycodes[] array
hw/nvram/xlnx-efuse-ctrl: Free XlnxVersalEFuseCtrl[] "pg0-lock" array
hw/nvram/xlnx-efuse: Free XlnxEFuse::ro_bits[] array on finalize()
hw/misc/mps2-scc: Free MPS2SCC::oscclk[] array on finalize()
hw/virtio: Free VirtIOIOMMUPCI::vdev.reserved_regions[] on finalize()
hw/virtio: Add VirtioPCIDeviceTypeInfo::instance_finalize field
hw/net/can/xlnx-zynqmp: Avoid underflow while popping RX FIFO
hw/net/can/xlnx-zynqmp: Avoid underflow while popping TX FIFOs
target/arm: Handle overflow in calculation of next timer tick
target/arm: Set IL bit for pauth, SVE access, BTI trap syndromes
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 745c2911cc0a20da2e3a1e96ba0ae42a5ad65773
https://github.com/qemu/qemu/commit/745c2911cc0a20da2e3a1e96ba0ae42a5ad65773
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M docs/devel/s390-cpu-topology.rst
M hw/audio/via-ac97.c
M hw/avr/atmega.c
M hw/isa/vt82c686.c
M hw/usb/vt82c686-uhci-pci.c
M include/hw/isa/vt82c686.h
M target/avr/cpu.c
M target/avr/cpu.h
M target/hexagon/idef-parser/prepare
Log Message:
-----------
Merge tag 'misc-next-20231128' of https://github.com/philmd/qemu into staging
Misc fixes for 8.2
* buildsys: Invoke bash via 'env' (Samuel)
* doc: Fix example in s390-cpu-topology.rst (Zhao)
* HW: Fix AVR ATMega reset stack (Gihun) and VT82C686 IRQ routing (Zoltan)
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVl7MUACgkQ4+MsLN6t
# wN4nsQ//U7/GGrMaNJF369pC0UfC0dfD39RoD9jmmrWUQB17baMvXo+BMBcELX0Q
# BtgRjIYwnywnVZlB11JL5Ql9ykSRqd7VeqnZfH//GqQO+ySF7jl6ekNT6YNjUbWu
# iF9bU3o0/LAVl/3pe9LQ4q/yOjzERA5o4JKYviHZYcWE811/5lBNgER4iPyCz6a8
# aGI3S5PGmq6a9x5266jkY2WWldDy7D1ujkuvxxc4tgnmbBjL21soJ/oRLOBjGTNl
# hCRfDTEiFZm7OxjV7oB03Nr3EGGStGdy0aPhhtFwzZxQ9yV7d2DLsbYGgwzZYkKQ
# 9v4DtGqYyvDA7LBmfxOrnzL0WXgN4xO3qekLqHDtChDzFFEYwtHvH0duPUiQv1Yu
# qHyOsfB58rKzWHeo0ACEjMWGdD1opCXCeoJlEf/saiQ5EgyBwph/z2mWYN4yak5H
# Zu3xF15BcnyavC6sVeuE+rT574dhCzOtH8Vf3WVwqfL5D5cyCjHlmPSAXXMqBkmh
# BMOD8O210n6IdzuuOQ038t3yGvIc0YysOmQgfLjRYlZa884q3wExgrufH+NYbGMj
# bFthPjLKgHm+q4k2mH65G98xwXQFT6rdHanw2iEJcPJbhhk9SNWYgaQ0r0Oi2Pfd
# zCQ22F1j9UqGcqKh+8tzAfjayRyQUJtgizPXEWanADkpIDYxrRk=
# =323/
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 28 Nov 2023 08:36:05 EST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'misc-next-20231128' of https://github.com/philmd/qemu:
docs/s390: Fix wrong command example in s390-cpu-topology.rst
hw/avr/atmega: Fix wrong initial value of stack pointer
hw/audio/via-ac97: Route interrupts using via_isa_set_irq()
hw/isa/vt82c686: Route PIRQ inputs using via_isa_set_irq()
hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts
hw/isa/vt82c686: Bring back via_isa_set_irq()
target/hexagon/idef-parser/prepare: use env to invoke bash
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: abf635ddfe3242df907f58967f3c1e6763bbca2d
https://github.com/qemu/qemu/commit/abf635ddfe3242df907f58967f3c1e6763bbca2d
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M VERSION
Log Message:
-----------
Update version for v8.2.0-rc2 release
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/9155a938cf8f...abf635ddfe32