[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 560f25: tests/avocado/machine_aspeed.py: Upda
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 560f25: tests/avocado/machine_aspeed.py: Update buildroot ... |
|
Date: |
Fri, 02 Feb 2024 05:50:19 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 560f2541079ef32bd21fc80be31adc82705f9c79
https://github.com/qemu/qemu/commit/560f2541079ef32bd21fc80be31adc82705f9c79
Author: Cédric Le Goater <clg@kaod.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M tests/avocado/machine_aspeed.py
Log Message:
-----------
tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11
Compared to mainline buildroot, these images have some customization :
- Linux version is bumped to 6.6.3 and built with a custom config
- U-Boot is switched to the one provided by OpenBMC for more support
- defconfigs extra tools for dev
See branch [1] for more details.
There are a few changes since last update, commit ed1f5ff84209. Images
all have a password now and I2C devices have been updated in the Linux
ast2600-evb device tree [2]. Do the necessary adjustements.
[1] https://github.com/legoater/buildroot/commits/aspeed-2023.11
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9deb10cf160e
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2e3b9c937c50499eda41b68bd787f6b6863397f6
https://github.com/qemu/qemu/commit/2e3b9c937c50499eda41b68bd787f6b6863397f6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Remove dead code
Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed:
Adding new machine Tiogapass in QEMU").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0e42592823762ec6df596e765c174478bc20f0c7
https://github.com/qemu/qemu/commit/0e42592823762ec6df596e765c174478bc20f0c7
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
Since commit b7f1a0cb76 ("arm/aspeed: Compute the number
of CPUs from the SoC definition") Aspeed machines use the
aspeed_soc_num_cpus() helper to set the number of CPUs.
Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc:
Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e
"hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 43a0a5c9950edc2e194ef21c2deacc16df37179d
https://github.com/qemu/qemu/commit/43a0a5c9950edc2e194ef21c2deacc16df37179d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Init CPU defaults in a common helper
Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
helper to reduce code duplication.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d815649c512fc785508315ead66a43385cf55bfb
https://github.com/qemu/qemu/commit/d815649c512fc785508315ead66a43385cf55bfb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
In order to alter AspeedSoCClass::cpu_type in the next
commit, introduce the aspeed_soc_cpu_type() helper to
retrieve the per-SoC CPU type from AspeedSoCClass.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: dc13909ed03c05275deb32512e9d8f8e34d79c3b
https://github.com/qemu/qemu/commit/dc13909ed03c05275deb32512e9d8f8e34d79c3b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Check for CPU types in machine_run_board_init()
Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
Convert it to a NULL-terminated array (of a single non-NULL element).
Set MachineClass::valid_cpu_types[] to use the common machine code
to provide hints when the requested CPU is invalid (see commit
e702cbc19e ("machine: Improve is_cpu_type_supported()").
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 99f0c046f46dae7a7ede7d298de429c3596e76e6
https://github.com/qemu/qemu/commit/99f0c046f46dae7a7ede7d298de429c3596e76e6
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/Kconfig
A hw/fsi/Kconfig
A hw/fsi/lbus.c
A hw/fsi/meson.build
A hw/fsi/trace-events
A hw/fsi/trace.h
M hw/meson.build
A include/hw/fsi/lbus.h
M meson.build
Log Message:
-----------
hw/fsi: Introduce IBM's Local bus
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain mapped memory for the devices. The
memory is mapped after CFAM config, peek table and FSI slave registers.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - removed lbus_add_device() bc unused
- removed lbus_create_device() bc used only once
- removed "address" property
- updated meson.build to build fsi dir
- included an empty hw/fsi/trace-events ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ca782334cb821a84d701133a6421516d264cf0d3
https://github.com/qemu/qemu/commit/ca782334cb821a84d701133a6421516d264cf0d3
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/fsi/lbus.c
M hw/fsi/trace-events
M include/hw/fsi/lbus.h
Log Message:
-----------
hw/fsi: Introduce IBM's scratchpad device
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The scratchpad provides a set of non-functional registers. The firmware
is free to use them, hardware does not support any special management
support. The scratchpad registers can be read or written from LBUS
slave. The scratch pad is managed under FSI CFAM state.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - moved object FSIScratchPad under FSICFAMState
- moved FSIScratchPad code under cfam.c ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f4de3ca160c897ed3157ab8f0ad33ed93fe4bfe0
https://github.com/qemu/qemu/commit/f4de3ca160c897ed3157ab8f0ad33ed93fe4bfe0
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A hw/fsi/fsi.c
M hw/fsi/meson.build
A include/hw/fsi/fsi.h
Log Message:
-----------
hw/fsi: Introduce IBM's FSI Bus
This is a part of patchset where FSI bus is introduced.
The FSI bus is a simple bus where FSI master is attached.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - removed include/hw/fsi/engine-scratchpad.h and
hw/fsi/engine-scratchpad.c
- dropped FSI_SCRATCHPAD
- included FSIBus definition
- dropped hw/fsi/trace-events changes ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6a2897bb5f28944997a0c8410b6d2ee162b9ae98
https://github.com/qemu/qemu/commit/6a2897bb5f28944997a0c8410b6d2ee162b9ae98
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/fsi/fsi.c
M hw/fsi/trace-events
M include/hw/fsi/fsi.h
Log Message:
-----------
hw/fsi: Introduce IBM's fsi-slave model
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The FSI slave: The slave is the terminal point of the FSI bus for
FSI symbols addressed to it. Slaves can be cascaded off of one
another. The slave's configuration registers appear in address space
of the CFAM to which it is attached.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f32f8e4d20b00e9b1fc1fcdd61050312d9ec75f6
https://github.com/qemu/qemu/commit/f32f8e4d20b00e9b1fc1fcdd61050312d9ec75f6
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A hw/fsi/cfam.c
M hw/fsi/meson.build
M hw/fsi/trace-events
A include/hw/fsi/cfam.h
Log Message:
-----------
hw/fsi: Introduce IBM's cfam
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang off of an internal Local Bus (LBUS) which is described
by the CFAM configuration block.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - moved object FSIScratchPad under FSICFAMState
- moved FSIScratchPad code under cfam.c
- introduced fsi_cfam_instance_init()
- reworked fsi_cfam_realize() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ca0331073722d27b033ca43a827f04fdf2a2bcce
https://github.com/qemu/qemu/commit/ca0331073722d27b033ca43a827f04fdf2a2bcce
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A hw/fsi/fsi-master.c
M hw/fsi/meson.build
M hw/fsi/trace-events
A include/hw/fsi/fsi-master.h
Log Message:
-----------
hw/fsi: Introduce IBM's FSI master
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI master. CFAM is hanging out of FSI master which is a
bus controller.
The FSI master: A controller in the platform service processor (e.g.
BMC) driving CFAM engine accesses into the POWER chip. At the
hardware level FSI is a bit-based protocol supporting synchronous and
DMA-driven accesses of engines in a CFAM.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - move FSICFAMState object under FSIMasterState
- introduced fsi_master_init()
- reworked fsi_master_realize()
- dropped FSIBus definition ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 27edd5040cae63bfa92c68f69883ba81aa3b6cda
https://github.com/qemu/qemu/commit/27edd5040cae63bfa92c68f69883ba81aa3b6cda
Author: Song Gao <gaosong@loongson.cn>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M target/loongarch/cpu.c
A target/loongarch/cpu_helper.c
M target/loongarch/internals.h
M target/loongarch/meson.build
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Fix qtest test-hmp error when KVM-only build
The cc->sysemu_ops->get_phys_page_debug() is NULL when
KVM-only build. this patch fixes it.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20240125061401.52526-1-gaosong@loongson.cn>
Commit: eb04c35da2c063515667e513028d64e27178365f
https://github.com/qemu/qemu/commit/eb04c35da2c063515667e513028d64e27178365f
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/arm/Kconfig
M hw/fsi/Kconfig
A hw/fsi/aspeed_apb2opb.c
M hw/fsi/meson.build
M hw/fsi/trace-events
A include/hw/fsi/aspeed_apb2opb.h
Log Message:
-----------
hw/fsi: Aspeed APB2OPB & On-chip peripheral bus
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses are indirect through the bridge.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI master IP with the OPB, mainly the
existence of an MMIO-mapping of the CFAM address straight onto a
sub-region of the OPB address space.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - moved FSIMasterState under AspeedAPB2OPBState
- modified fsi_opb_fsi_master_address() and
fsi_opb_opb2fsi_address()
- instroduced fsi_aspeed_apb2opb_init()
- reworked fsi_aspeed_apb2opb_realize()
- removed FSIMasterState object and fsi_opb_realize()
- simplified OPBus
- introduced fsi_aspeed_apb2opb_rw to fix endianness issue ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3fd941f3f10da2d3c08cac4f183b76b2388b7c53
https://github.com/qemu/qemu/commit/3fd941f3f10da2d3c08cac4f183b76b2388b7c53
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M hw/arm/aspeed_ast2600.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm: Hook up FSI module in AST2600
This patchset introduces IBM's Flexible Service Interface(FSI).
Time for some fun with inter-processor buses. FSI allows a service
processor access to the internal buses of a host POWER processor to
perform configuration or debugging.
FSI has long existed in POWER processes and so comes with some baggage,
including how it has been integrated into the ASPEED SoC.
Working backwards from the POWER processor, the fundamental pieces of
interest for the implementation are:
1. The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on buses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang off of an internal Local Bus (LBUS) which is described
by the CFAM configuration block.
2. The FSI slave: The slave is the terminal point of the FSI bus for
FSI symbols addressed to it. Slaves can be cascaded off of one
another. The slave's configuration registers appear in address space
of the CFAM to which it is attached.
3. The FSI master: A controller in the platform service processor (e.g.
BMC) driving CFAM engine accesses into the POWER chip. At the
hardware level FSI is a bit-based protocol supporting synchronous and
DMA-driven accesses of engines in a CFAM.
4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI master IP with the OPB, mainly the
existence of an MMIO-mapping of the CFAM address straight onto a
sub-region of the OPB address space.
5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses are indirect through the bridge.
The implementation appears as following in the qemu device tree:
(qemu) info qtree
bus: main-system-bus
type System
...
dev: aspeed.apb2opb, id ""
gpio-out "sysbus-irq" 1
mmio 000000001e79b000/0000000000001000
bus: opb.1
type opb
dev: fsi.master, id ""
bus: fsi.bus.1
type fsi.bus
dev: cfam.config, id ""
dev: cfam, id ""
bus: fsi.lbus.1
type lbus
dev: scratchpad, id ""
address = 0 (0x0)
bus: opb.0
type opb
dev: fsi.master, id ""
bus: fsi.bus.0
type fsi.bus
dev: cfam.config, id ""
dev: cfam, id ""
bus: fsi.lbus.0
type lbus
dev: scratchpad, id ""
address = 0 (0x0)
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically generate the CFAM
configuration block. The configuration block presents engines in the
order they are attached to the CFAM's LBUS. Engine implementations
should subclass the LBusDevice and set the 'config' member of
LBusDeviceClass to match the engine's type.
CFAM designs offer a lot of flexibility, for instance it is possible for
a CFAM to be simultaneously driven from multiple FSI links. The modeling
is not so complete; it's assumed that each CFAM is attached to a single
FSI slave (as a consequence the CFAM subclasses the FSI slave).
As for FSI, its symbols and wire-protocol are not modelled at all. This
is not necessary to get FSI off the ground thanks to the mapping of the
CFAM address space onto the OPB address space - the models follow this
directly and map the CFAM memory region into the OPB's memory region.
Future work includes supporting more advanced accesses that drive the
FSI master directly rather than indirectly via the CFAM mapping, which
will require implementing the FSI state machine and methods for each of
the FSI symbols on the slave. Further down the track we can also look at
supporting the bitbanged SoftFSI drivers in Linux by extending the FSI
slave model to resolve sequences of GPIO IRQs into FSI symbols, and
calling the associated symbol method on the slave to map the access onto
the CFAM.
Testing:
Tested by reading cfam config address 0 on rainier machine type.
root@p10bmc:~# pdbg -a getcfam 0x0
p0: 0x0 = 0xc0022d15
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 45d8cdbd562e1752ee8826beae1e35756d998445
https://github.com/qemu/qemu/commit/45d8cdbd562e1752ee8826beae1e35756d998445
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A tests/qtest/aspeed_fsi-test.c
M tests/qtest/meson.build
Log Message:
-----------
hw/fsi: Added qtest
Added basic qtests for FSI model.
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Acked-by: Thomas Huth <thuth@redhat.com>
[ clg: aspeed-fsi-test.c -> aspeed_fsi-test.c to match other filenames ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9f70e83ae64ed2aead57ea838f23c215831c2f74
https://github.com/qemu/qemu/commit/9f70e83ae64ed2aead57ea838f23c215831c2f74
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A docs/specs/fsi.rst
M docs/specs/index.rst
Log Message:
-----------
hw/fsi: Added FSI documentation
Documentation for IBM FSI model.
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : - Removed source file list
- Fixed aspeed machine reference ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 649b8ed20543f1b7f7e3dd8fd409092639bb345e
https://github.com/qemu/qemu/commit/649b8ed20543f1b7f7e3dd8fd409092639bb345e
Author: Ninad Palsule <ninad@linux.ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
hw/fsi: Update MAINTAINER list
Add maintainer for IBM FSI model
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - slight change in commit log
- fixed file list ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 89c958c120bcd10458d4cf2e0237cae31a14223b
https://github.com/qemu/qemu/commit/89c958c120bcd10458d4cf2e0237cae31a14223b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M target/loongarch/cpu.c
A target/loongarch/cpu_helper.c
M target/loongarch/internals.h
M target/loongarch/meson.build
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
Merge tag 'pull-loongarch-20240201' of https://gitlab.com/gaosong/qemu into
staging
pull-loongarch-20240201
# -----BEGIN PGP SIGNATURE-----
#
# iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZbtI0AAKCRBAov/yOSY+
# 35J4A/9ehl15MIrkByqq8QNQnG4PbKWOTcTev6P0sEAhzPUtBpcGPesoHnt+DFuk
# f3WluWsfnFY9pCRgB9VBSpy89O6Efj187bpekT/PD5svPOXoUmETafv1p2vsVrpj
# huMNijt7I/LAXUCb2gA5pnNH9vrrJ8E5kQlgmYfh35cEhHObMQ==
# =Q9Gn
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 01 Feb 2024 07:31:28 GMT
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-20240201' of https://gitlab.com/gaosong/qemu:
target/loongarch: Fix qtest test-hmp error when KVM-only build
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c3709fde5955d13f6d4f86ab46ef3cc2288ca65e
https://github.com/qemu/qemu/commit/c3709fde5955d13f6d4f86ab46ef3cc2288ca65e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M MAINTAINERS
A docs/specs/fsi.rst
M docs/specs/index.rst
M hw/Kconfig
M hw/arm/Kconfig
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc_common.c
A hw/fsi/Kconfig
A hw/fsi/aspeed_apb2opb.c
A hw/fsi/cfam.c
A hw/fsi/fsi-master.c
A hw/fsi/fsi.c
A hw/fsi/lbus.c
A hw/fsi/meson.build
A hw/fsi/trace-events
A hw/fsi/trace.h
M hw/meson.build
M include/hw/arm/aspeed_soc.h
A include/hw/fsi/aspeed_apb2opb.h
A include/hw/fsi/cfam.h
A include/hw/fsi/fsi-master.h
A include/hw/fsi/fsi.h
A include/hw/fsi/lbus.h
M meson.build
M tests/avocado/machine_aspeed.py
A tests/qtest/aspeed_fsi-test.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Update of buildroot images to 2023.11 (6.6.3 kernel)
* Check of the valid CPU type supported by aspeed machines
* Simplified models for the IBM's FSI bus and the Aspeed
controller bridge
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7
# 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD
# lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q
# 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb
# 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj
# wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI
# yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo
# ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH
# 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ
# 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/
# 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb
# D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo=
# =0C5S
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 01 Feb 2024 07:35:11 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu:
hw/fsi: Update MAINTAINER list
hw/fsi: Added FSI documentation
hw/fsi: Added qtest
hw/arm: Hook up FSI module in AST2600
hw/fsi: Aspeed APB2OPB & On-chip peripheral bus
hw/fsi: Introduce IBM's FSI master
hw/fsi: Introduce IBM's cfam
hw/fsi: Introduce IBM's fsi-slave model
hw/fsi: Introduce IBM's FSI Bus
hw/fsi: Introduce IBM's scratchpad device
hw/fsi: Introduce IBM's Local bus
hw/arm/aspeed: Check for CPU types in machine_run_board_init()
hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
hw/arm/aspeed: Init CPU defaults in a common helper
hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
hw/arm/aspeed: Remove dead code
tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/14639717bf37...c3709fde5955