[Qemu-devel] [PATCH 4/6] target/mips: Correct the second argument type of cpu_supports_isa()

[Aleksandar Markovic]

From: Aleksandar Markovic <address@hidden>

"insn_flags" bitfield was expanded from 32-bit to 64-bit at one moment.
However, this was not reflected at the second argument of the function
cpu_supports_isa(). By chance, this did not create a wrong behavior,
since the second argument was always with the left-most half zero, but
it is still a bug waiting to happen. correct by changint the type of
the second argument to be 64-bit always.

Signed-off-by: Aleksandar Markovic <address@hidden>
---
 target/mips/cpu.h       | 2 +-
 target/mips/translate.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 03c03fd..fd22bd5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1011,7 +1011,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, 
void *puc);
 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
 
 bool cpu_supports_cps_smp(const char *cpu_type);
-bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
+bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
 void cpu_set_exception_base(int vp_index, target_ulong address);
 
 /* mips_int.c */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ceaa582..b660235 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29803,7 +29803,7 @@ bool cpu_supports_cps_smp(const char *cpu_type)
     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 }
 
-bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
+bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
 {
     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
     return (mcc->cpu_def->insn_flags & isa) != 0;
-- 
2.7.4