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[Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system()
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system() |
Date: |
Tue, 22 Jan 2019 10:29:03 +0100 |
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/translate.c | 31 -------------------------------
1 file changed, 31 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d0b0fca12b..0e37beb68e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -427,32 +427,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int csr)
-{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- }
-}
static void decode_RV32_64C0(DisasContext *ctx)
{
@@ -628,7 +602,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
{
- int rs1, rd;
uint32_t op;
/* We do not do misaligned address check here: the address should never be
@@ -637,13 +610,9 @@ static void decode_RV32_64G(CPURISCVState *env,
DisasContext *ctx)
* perform the misaligned instruction fetch */
op = MASK_OP_MAJOR(ctx->opcode);
- rs1 = GET_RS1(ctx->opcode);
- rd = GET_RD(ctx->opcode);
switch (op) {
case OPC_RISC_SYSTEM:
- gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
break;
default:
gen_exception_illegal(ctx);
--
2.20.1
- [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G(), (continued)
- [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system(),
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/22