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Re: [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() dec
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions |
Date: |
Tue, 22 Jan 2019 13:36:20 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> gen_arith_imm() does a lot of decoding manually, which was hard to read
> in case of the shift instructions and is not necessary anymore with
> decodetree.
>
> Signed-off-by: Bastian Koppelmann <address@hidden>
> Signed-off-by: Peer Adelt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
Watch the funky indentation.
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> +
> + tcg_gen_sari_tl(t, t, a->shamt);
> + gen_set_gpr(a->rd, t);
Likewise.
r~
- [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, (continued)
- [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/22
- Re: [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions,
Richard Henderson <=
- [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2019/01/22