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Re: [Qemu-devel] [PULL 00/49] target-arm queue


From: no-reply
Subject: Re: [Qemu-devel] [PULL 00/49] target-arm queue
Date: Thu, 31 Jan 2019 09:48:11 -0800 (PST)

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PULL 00/49] target-arm queue
Type: series
Message-id: address@hidden

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
dc264dd9a4 tests/libqtest: Introduce qtest_init_with_serial()
00a3d5ff24 target/arm: Implement PMSWINC
1367cbdcd9 target/arm: PMU: Set PMCR.N to 4
ec6f7cc59a target/arm: PMU: Add instruction and cycle events
2d86ff3ae5 target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
c231717c50 target/arm: Add array for supported PMU events, generate 
PMCEID[01]_EL0
9760098cad target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
d29040fb38 target/arm: Define FIELDs for ID_DFR0
89baa1c6e0 target/arm: Implement PMOVSSET
d53dc888d1 target/arm: Allow AArch32 access for PMCCFILTR
9638f29e02 target/arm: Filter cycle counter based on PMCCFILTR_EL0
3e0db1e655 target/arm: Swap PMU values before/after migrations
5a8ad937a1 target/arm: Reorganize PMCCNTR accesses
002e2a459e migration: Add post_save function to VMStateDescription
3c00592eb7 target/arm: Tidy TBI handling in gen_a64_set_pc
24e28d6a3a target/arm: Enable PAuth for user-only
fbf675bf14 target/arm: Enable PAuth for -cpu max
789d26ba5d target/arm: Add PAuth system registers
fc4ea461df target/arm: Implement pauth_computepac
0f4ee384b6 target/arm: Implement pauth_addpac
5d622eb1de target/arm: Implement pauth_auth
6ef77a0dbf target/arm: Implement pauth_strip
4db3223298 target/arm: Reuse aa64_va_parameters for setting tbflags
37911b85ec target/arm: Decode TBID from TCR
45ff620692 target/arm: Add aa64_va_parameters_both
60da4cfb8e target/arm: Export aa64_va_parameters to internals.h
9f6d40cbc7 target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
d82bb524a6 target/arm: Create ARMVAParameters and helpers
1c1d89edb6 target/arm: Introduce arm_stage1_mmu_idx
e50f90142a target/arm: Introduce arm_mmu_idx
1816b8d727 target/arm: Move cpu_mmu_index out of line
a0033e2e8f target/arm: Decode Load/store register (pac)
7f26a158f1 target/arm: Decode PAuth within disas_uncond_b_reg
ab96f95f08 target/arm: Rearrange decode in disas_uncond_b_reg
c6f29a64cb target/arm: Add new_pc argument to helper_exception_return
00505a3d3b target/arm: Move helper_exception_return to helper-a64.c
f1cd15ed3d target/arm: Decode PAuth within disas_data_proc_2src
186ce5b0aa target/arm: Decode PAuth within disas_data_proc_1src
6e4cf8f308 target/arm: Rearrange decode in disas_data_proc_1src
1b5190aa4b target/arm: Decode PAuth within system hint space
9f6f95c13a target/arm: Add PAuth helpers
2ab95bf605 target/arm: Introduce raise_exception_ra
7d47196774 target/arm: Add PAuth active bit to tbflags
eb274837e8 target/arm: Add SCTLR bits through ARMv8.5
c1bb33ecce target/arm: Add state for the ARMv8.3-PAuth extension
a5be306757 ftgmac100: implement the new MDIO interface on Aspeed SoC
20c6f95af2 target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
1731fb6c58 hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
f9b569ab06 hw/char/stm32f2xx_usart: Do not update data register when device is 
disabled

=== OUTPUT BEGIN ===
1/49 Checking commit f9b569ab06af (hw/char/stm32f2xx_usart: Do not update data 
register when device is disabled)
2/49 Checking commit 1731fb6c5864 (hw/arm/virt-acpi-build: Set COHACC override 
flag in IORT SMMUv3 node)
3/49 Checking commit 20c6f95af2a0 (target/arm: Allow Aarch32 exception return 
to switch from Mon->Hyp)
4/49 Checking commit a5be3067572d (ftgmac100: implement the new MDIO interface 
on Aspeed SoC)
5/49 Checking commit c1bb33ecce31 (target/arm: Add state for the ARMv8.3-PAuth 
extension)
6/49 Checking commit eb274837e818 (target/arm: Add SCTLR bits through ARMv8.5)
7/49 Checking commit 7d4719677443 (target/arm: Add PAuth active bit to tbflags)
8/49 Checking commit 2ab95bf605bb (target/arm: Introduce raise_exception_ra)
9/49 Checking commit 9f6f95c13a25 (target/arm: Add PAuth helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#73: 
new file mode 100644

total: 0 errors, 1 warnings, 226 lines checked

Patch 9/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/49 Checking commit 1b5190aa4be1 (target/arm: Decode PAuth within system hint 
space)
11/49 Checking commit 6e4cf8f308e7 (target/arm: Rearrange decode in 
disas_data_proc_1src)
12/49 Checking commit 186ce5b0aa7c (target/arm: Decode PAuth within 
disas_data_proc_1src)
13/49 Checking commit f1cd15ed3df3 (target/arm: Decode PAuth within 
disas_data_proc_2src)
14/49 Checking commit 00505a3d3be5 (target/arm: Move helper_exception_return to 
helper-a64.c)
WARNING: Block comments use a leading /* on a separate line
#25: FILE: target/arm/helper-a64.c:892:
+    /* Return the exception level that this SPSR is requesting a return to,

WARNING: Block comments use a leading /* on a separate line
#42: FILE: target/arm/helper-a64.c:909:
+            /* Returning to Mon from AArch64 is never possible,

WARNING: Block comments use a leading /* on a separate line
#73: FILE: target/arm/helper-a64.c:940:
+    /* We must squash the PSTATE.SS bit to zero unless both of the

WARNING: Block comments use a leading /* on a separate line
#90: FILE: target/arm/helper-a64.c:957:
+        /* Disallow return to an EL which is unimplemented or higher

WARNING: Block comments use a leading /* on a separate line
#116: FILE: target/arm/helper-a64.c:983:
+        /* We do a raw CPSR write because aarch64_sync_64_to_32()

WARNING: Block comments use a leading /* on a separate line
#159: FILE: target/arm/helper-a64.c:1026:
+    /* Illegal return events of various kinds have architecturally

total: 0 errors, 6 warnings, 337 lines checked

Patch 14/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/49 Checking commit c6f29a64cb80 (target/arm: Add new_pc argument to 
helper_exception_return)
16/49 Checking commit ab96f95f0865 (target/arm: Rearrange decode in 
disas_uncond_b_reg)
17/49 Checking commit 7f26a158f181 (target/arm: Decode PAuth within 
disas_uncond_b_reg)
18/49 Checking commit a0033e2e8f58 (target/arm: Decode Load/store register 
(pac))
WARNING: Block comments use a leading /* on a separate line
#74: FILE: target/arm/translate-a64.c:3198:
+    do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false,

WARNING: Block comments use a leading /* on a separate line
#75: FILE: target/arm/translate-a64.c:3199:
+              /* extend */ false, /* iss_valid */ !is_wback,

WARNING: Block comments use a leading /* on a separate line
#76: FILE: target/arm/translate-a64.c:3200:
+              /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);

total: 0 errors, 3 warnings, 73 lines checked

Patch 18/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/49 Checking commit 1816b8d72764 (target/arm: Move cpu_mmu_index out of line)
20/49 Checking commit e50f90142a9f (target/arm: Introduce arm_mmu_idx)
WARNING: Block comments use a leading /* on a separate line
#31: FILE: target/arm/cpu.h:2752:
+/**

WARNING: Block comments use a leading /* on a separate line
#121: FILE: target/arm/internals.h:922:
+/**

total: 0 errors, 2 warnings, 90 lines checked

Patch 20/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/49 Checking commit 1c1d89edb6b5 (target/arm: Introduce arm_stage1_mmu_idx)
WARNING: Block comments use a leading /* on a separate line
#42: FILE: target/arm/internals.h:930:
+/**

total: 0 errors, 1 warnings, 32 lines checked

Patch 21/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
22/49 Checking commit d82bb524a63d (target/arm: Create ARMVAParameters and 
helpers)
ERROR: spaces prohibited around that ':' (ctx:WxW)
#376: FILE: target/arm/internals.h:950:
+    unsigned tsz    : 8;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#377: FILE: target/arm/internals.h:951:
+    unsigned select : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#378: FILE: target/arm/internals.h:952:
+    bool tbi        : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#379: FILE: target/arm/internals.h:953:
+    bool epd        : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#380: FILE: target/arm/internals.h:954:
+    bool hpd        : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#381: FILE: target/arm/internals.h:955:
+    bool using16k   : 1;
                     ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#382: FILE: target/arm/internals.h:956:
+    bool using64k   : 1;
                     ^

total: 7 errors, 0 warnings, 354 lines checked

Patch 22/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

23/49 Checking commit 9f6d40cbc750 (target/arm: Merge TBFLAG_AA_TB{0, 1} to 
TBII)
24/49 Checking commit 60da4cfb8e6d (target/arm: Export aa64_va_parameters to 
internals.h)
25/49 Checking commit 45ff620692b8 (target/arm: Add aa64_va_parameters_both)
26/49 Checking commit 37911b85ec73 (target/arm: Decode TBID from TCR)
ERROR: spaces prohibited around that ':' (ctx:WxW)
#87: FILE: target/arm/internals.h:953:
+    bool tbid       : 1;
                     ^

total: 1 errors, 0 warnings, 60 lines checked

Patch 26/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

27/49 Checking commit 4db3223298d6 (target/arm: Reuse aa64_va_parameters for 
setting tbflags)
28/49 Checking commit 6ef77a0dbf11 (target/arm: Implement pauth_strip)
29/49 Checking commit 5d622eb1de2d (target/arm: Implement pauth_auth)
30/49 Checking commit 0f4ee384b685 (target/arm: Implement pauth_addpac)
31/49 Checking commit fc4ea461dfc5 (target/arm: Implement pauth_computepac)
32/49 Checking commit 789d26ba5d8a (target/arm: Add PAuth system registers)
33/49 Checking commit fbf675bf14bf (target/arm: Enable PAuth for -cpu max)
34/49 Checking commit 24e28d6a3adf (target/arm: Enable PAuth for user-only)
35/49 Checking commit 3c00592eb7ea (target/arm: Tidy TBI handling in 
gen_a64_set_pc)
36/49 Checking commit 002e2a459e51 (migration: Add post_save function to 
VMStateDescription)
37/49 Checking commit 5a8ad937a141 (target/arm: Reorganize PMCCNTR accesses)
WARNING: Block comments use a leading /* on a separate line
#33: FILE: target/arm/cpu.h:476:
+        /* Stores the architectural value of the counter *the last time it was

WARNING: Block comments use a leading /* on a separate line
#39: FILE: target/arm/cpu.h:482:
+        /* Stores the delta between the architectural value and the underlying

WARNING: Block comments use a leading /* on a separate line
#70: FILE: target/arm/cpu.h:994:
+/**

total: 0 errors, 3 warnings, 217 lines checked

Patch 37/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
38/49 Checking commit 3e0db1e65591 (target/arm: Swap PMU values before/after 
migrations)
39/49 Checking commit 9638f29e02e9 (target/arm: Filter cycle counter based on 
PMCCFILTR_EL0)
WARNING: Block comments use a leading /* on a separate line
#41: FILE: target/arm/cpu.h:1005:
+/**

WARNING: Block comments use a leading /* on a separate line
#102: FILE: target/arm/helper.c:1092:
+/* Returns true if the counter (pass 31 for PMCCNTR) should count events using

total: 0 errors, 2 warnings, 178 lines checked

Patch 39/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
40/49 Checking commit d53dc888d187 (target/arm: Allow AArch32 access for 
PMCCFILTR)
41/49 Checking commit 89baa1c6e08b (target/arm: Implement PMOVSSET)
42/49 Checking commit d29040fb38b6 (target/arm: Define FIELDs for ID_DFR0)
43/49 Checking commit 9760098cadc2 (target/arm: Make PMCEID[01]_EL0 64 bit 
registers, add PMCEID[23])
44/49 Checking commit c231717c50b1 (target/arm: Add array for supported PMU 
events, generate PMCEID[01]_EL0)
45/49 Checking commit 2d86ff3ae545 (target/arm: Finish implementation of 
PM[X]EVCNTR and PM[X]EVTYPER)
WARNING: Block comments use a leading /* on a separate line
#307: FILE: target/arm/helper.c:1604:
+      /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR

WARNING: Block comments use a trailing */ on a separate line
#308: FILE: target/arm/helper.c:1605:
+       * are CONSTRAINED UNPREDICTABLE. */

total: 0 errors, 2 warnings, 406 lines checked

Patch 45/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
46/49 Checking commit ec6f7cc59aa3 (target/arm: PMU: Add instruction and cycle 
events)
WARNING: Block comments use a leading /* on a separate line
#57: FILE: target/arm/helper.c:1047:
+    return use_icount == 1 /* Precise instruction counting */;

total: 0 errors, 1 warnings, 151 lines checked

Patch 46/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
47/49 Checking commit 1367cbdcd990 (target/arm: PMU: Set PMCR.N to 4)
48/49 Checking commit 00a3d5ff24fe (target/arm: Implement PMSWINC)
49/49 Checking commit dc264dd9a4ef (tests/libqtest: Introduce 
qtest_init_with_serial())
WARNING: Block comments use a leading /* on a separate line
#60: FILE: tests/libqtest.h:65:
+/**

total: 0 errors, 1 warnings, 49 lines checked

Patch 49/49 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
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