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Re: [Qemu-devel] [PATCH] tests: Disable ipmi-bt-test
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Re: [Qemu-devel] [PATCH] tests: Disable ipmi-bt-test |
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Date: |
Thu, 31 Jan 2019 10:14:01 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH] tests: Disable ipmi-bt-test
Type: series
Message-id: address@hidden
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
dcd6a39df1 Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20190121' into staging
deb04bb051 target/arm: Implement PMSWINC
f437a7e648 target/arm: PMU: Set PMCR.N to 4
453d2ab0af target/arm: PMU: Add instruction and cycle events
70a3636dba target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
16665123e9 target/arm: Add array for supported PMU events, generate
PMCEID[01]_EL0
04c02317de target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
ee9c772092 target/arm: Define FIELDs for ID_DFR0
730070eb4f target/arm: Implement PMOVSSET
d7049d2d7c target/arm: Allow AArch32 access for PMCCFILTR
cc4ab8d374 target/arm: Filter cycle counter based on PMCCFILTR_EL0
192a68e0ea target/arm: Swap PMU values before/after migrations
1a65d2606d target/arm: Reorganize PMCCNTR accesses
72076e9f33 migration: Add post_save function to VMStateDescription
f21ab20ac6 target/arm: Tidy TBI handling in gen_a64_set_pc
c0d9fc7719 target/arm: Enable PAuth for user-only
dc094ab4f2 target/arm: Enable PAuth for -cpu max
ef9d9a852b target/arm: Add PAuth system registers
f5dacde5bc target/arm: Implement pauth_computepac
ce86bb5332 target/arm: Implement pauth_addpac
f085eaa123 target/arm: Implement pauth_auth
8a73f19b50 target/arm: Implement pauth_strip
d1708540f9 target/arm: Reuse aa64_va_parameters for setting tbflags
4c04282d03 target/arm: Decode TBID from TCR
b06859ff59 target/arm: Add aa64_va_parameters_both
dfcdc5d81a target/arm: Export aa64_va_parameters to internals.h
e3a01194f3 target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
be1fea6e10 target/arm: Create ARMVAParameters and helpers
d0a9eaa7d7 target/arm: Introduce arm_stage1_mmu_idx
13aaa4b00f target/arm: Introduce arm_mmu_idx
21e4e7e08d target/arm: Move cpu_mmu_index out of line
b95279a855 target/arm: Decode Load/store register (pac)
a422431846 target/arm: Decode PAuth within disas_uncond_b_reg
2f1cf45ddf target/arm: Rearrange decode in disas_uncond_b_reg
21fd57bec4 target/arm: Add new_pc argument to helper_exception_return
41d258ba8d target/arm: Move helper_exception_return to helper-a64.c
8a2c7ead1b target/arm: Decode PAuth within disas_data_proc_2src
fd93d915b4 target/arm: Decode PAuth within disas_data_proc_1src
77d9263f6c target/arm: Rearrange decode in disas_data_proc_1src
7c5c968fd2 target/arm: Decode PAuth within system hint space
7c98822b22 target/arm: Add PAuth helpers
a00a17e910 target/arm: Introduce raise_exception_ra
2eee8602e5 target/arm: Add PAuth active bit to tbflags
647fbdcd05 target/arm: Add SCTLR bits through ARMv8.5
ce4d63ba7d target/arm: Add state for the ARMv8.3-PAuth extension
1f759e86bd ftgmac100: implement the new MDIO interface on Aspeed SoC
40513c4da1 target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
1038687130 hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
7d1cfcd45c hw/char/stm32f2xx_usart: Do not update data register when device is
disabled
=== OUTPUT BEGIN ===
1/48 Checking commit 7d1cfcd45c89 (hw/char/stm32f2xx_usart: Do not update data
register when device is disabled)
2/48 Checking commit 103868713074 (hw/arm/virt-acpi-build: Set COHACC override
flag in IORT SMMUv3 node)
3/48 Checking commit 40513c4da128 (target/arm: Allow Aarch32 exception return
to switch from Mon->Hyp)
4/48 Checking commit 1f759e86bd54 (ftgmac100: implement the new MDIO interface
on Aspeed SoC)
5/48 Checking commit ce4d63ba7d65 (target/arm: Add state for the ARMv8.3-PAuth
extension)
6/48 Checking commit 647fbdcd059a (target/arm: Add SCTLR bits through ARMv8.5)
7/48 Checking commit 2eee8602e5d2 (target/arm: Add PAuth active bit to tbflags)
8/48 Checking commit a00a17e91079 (target/arm: Introduce raise_exception_ra)
9/48 Checking commit 7c98822b2285 (target/arm: Add PAuth helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#76:
new file mode 100644
total: 0 errors, 1 warnings, 226 lines checked
Patch 9/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/48 Checking commit 7c5c968fd2f6 (target/arm: Decode PAuth within system hint
space)
11/48 Checking commit 77d9263f6cd7 (target/arm: Rearrange decode in
disas_data_proc_1src)
12/48 Checking commit fd93d915b4ce (target/arm: Decode PAuth within
disas_data_proc_1src)
13/48 Checking commit 8a2c7ead1bfa (target/arm: Decode PAuth within
disas_data_proc_2src)
14/48 Checking commit 41d258ba8d19 (target/arm: Move helper_exception_return to
helper-a64.c)
WARNING: Block comments use a leading /* on a separate line
#28: FILE: target/arm/helper-a64.c:892:
+ /* Return the exception level that this SPSR is requesting a return to,
WARNING: Block comments use a leading /* on a separate line
#45: FILE: target/arm/helper-a64.c:909:
+ /* Returning to Mon from AArch64 is never possible,
WARNING: Block comments use a leading /* on a separate line
#76: FILE: target/arm/helper-a64.c:940:
+ /* We must squash the PSTATE.SS bit to zero unless both of the
WARNING: Block comments use a leading /* on a separate line
#93: FILE: target/arm/helper-a64.c:957:
+ /* Disallow return to an EL which is unimplemented or higher
WARNING: Block comments use a leading /* on a separate line
#119: FILE: target/arm/helper-a64.c:983:
+ /* We do a raw CPSR write because aarch64_sync_64_to_32()
WARNING: Block comments use a leading /* on a separate line
#162: FILE: target/arm/helper-a64.c:1026:
+ /* Illegal return events of various kinds have architecturally
total: 0 errors, 6 warnings, 337 lines checked
Patch 14/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/48 Checking commit 21fd57bec431 (target/arm: Add new_pc argument to
helper_exception_return)
16/48 Checking commit 2f1cf45ddf5b (target/arm: Rearrange decode in
disas_uncond_b_reg)
17/48 Checking commit a4224318463f (target/arm: Decode PAuth within
disas_uncond_b_reg)
18/48 Checking commit b95279a8556b (target/arm: Decode Load/store register
(pac))
WARNING: Block comments use a leading /* on a separate line
#77: FILE: target/arm/translate-a64.c:3198:
+ do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false,
WARNING: Block comments use a leading /* on a separate line
#78: FILE: target/arm/translate-a64.c:3199:
+ /* extend */ false, /* iss_valid */ !is_wback,
WARNING: Block comments use a leading /* on a separate line
#79: FILE: target/arm/translate-a64.c:3200:
+ /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);
total: 0 errors, 3 warnings, 73 lines checked
Patch 18/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/48 Checking commit 21e4e7e08d27 (target/arm: Move cpu_mmu_index out of line)
20/48 Checking commit 13aaa4b00f3f (target/arm: Introduce arm_mmu_idx)
WARNING: Block comments use a leading /* on a separate line
#34: FILE: target/arm/cpu.h:2752:
+/**
WARNING: Block comments use a leading /* on a separate line
#124: FILE: target/arm/internals.h:922:
+/**
total: 0 errors, 2 warnings, 90 lines checked
Patch 20/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/48 Checking commit d0a9eaa7d774 (target/arm: Introduce arm_stage1_mmu_idx)
WARNING: Block comments use a leading /* on a separate line
#45: FILE: target/arm/internals.h:930:
+/**
total: 0 errors, 1 warnings, 32 lines checked
Patch 21/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
22/48 Checking commit be1fea6e1028 (target/arm: Create ARMVAParameters and
helpers)
ERROR: spaces prohibited around that ':' (ctx:WxW)
#379: FILE: target/arm/internals.h:950:
+ unsigned tsz : 8;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#380: FILE: target/arm/internals.h:951:
+ unsigned select : 1;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#381: FILE: target/arm/internals.h:952:
+ bool tbi : 1;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#382: FILE: target/arm/internals.h:953:
+ bool epd : 1;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#383: FILE: target/arm/internals.h:954:
+ bool hpd : 1;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#384: FILE: target/arm/internals.h:955:
+ bool using16k : 1;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#385: FILE: target/arm/internals.h:956:
+ bool using64k : 1;
^
total: 7 errors, 0 warnings, 354 lines checked
Patch 22/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
23/48 Checking commit e3a01194f39d (target/arm: Merge TBFLAG_AA_TB{0, 1} to
TBII)
24/48 Checking commit dfcdc5d81a82 (target/arm: Export aa64_va_parameters to
internals.h)
25/48 Checking commit b06859ff5929 (target/arm: Add aa64_va_parameters_both)
26/48 Checking commit 4c04282d0316 (target/arm: Decode TBID from TCR)
ERROR: spaces prohibited around that ':' (ctx:WxW)
#90: FILE: target/arm/internals.h:953:
+ bool tbid : 1;
^
total: 1 errors, 0 warnings, 60 lines checked
Patch 26/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
27/48 Checking commit d1708540f91b (target/arm: Reuse aa64_va_parameters for
setting tbflags)
28/48 Checking commit 8a73f19b50de (target/arm: Implement pauth_strip)
29/48 Checking commit f085eaa123f6 (target/arm: Implement pauth_auth)
30/48 Checking commit ce86bb5332a9 (target/arm: Implement pauth_addpac)
31/48 Checking commit f5dacde5bcee (target/arm: Implement pauth_computepac)
32/48 Checking commit ef9d9a852bfc (target/arm: Add PAuth system registers)
33/48 Checking commit dc094ab4f2b9 (target/arm: Enable PAuth for -cpu max)
34/48 Checking commit c0d9fc7719d0 (target/arm: Enable PAuth for user-only)
35/48 Checking commit f21ab20ac607 (target/arm: Tidy TBI handling in
gen_a64_set_pc)
36/48 Checking commit 72076e9f3341 (migration: Add post_save function to
VMStateDescription)
37/48 Checking commit 1a65d2606d0c (target/arm: Reorganize PMCCNTR accesses)
WARNING: Block comments use a leading /* on a separate line
#36: FILE: target/arm/cpu.h:476:
+ /* Stores the architectural value of the counter *the last time it was
WARNING: Block comments use a leading /* on a separate line
#42: FILE: target/arm/cpu.h:482:
+ /* Stores the delta between the architectural value and the underlying
WARNING: Block comments use a leading /* on a separate line
#73: FILE: target/arm/cpu.h:994:
+/**
total: 0 errors, 3 warnings, 217 lines checked
Patch 37/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
38/48 Checking commit 192a68e0ea69 (target/arm: Swap PMU values before/after
migrations)
39/48 Checking commit cc4ab8d3745f (target/arm: Filter cycle counter based on
PMCCFILTR_EL0)
WARNING: Block comments use a leading /* on a separate line
#44: FILE: target/arm/cpu.h:1005:
+/**
WARNING: Block comments use a leading /* on a separate line
#105: FILE: target/arm/helper.c:1092:
+/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
total: 0 errors, 2 warnings, 178 lines checked
Patch 39/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
40/48 Checking commit d7049d2d7c32 (target/arm: Allow AArch32 access for
PMCCFILTR)
41/48 Checking commit 730070eb4f73 (target/arm: Implement PMOVSSET)
42/48 Checking commit ee9c772092e3 (target/arm: Define FIELDs for ID_DFR0)
43/48 Checking commit 04c02317de86 (target/arm: Make PMCEID[01]_EL0 64 bit
registers, add PMCEID[23])
44/48 Checking commit 16665123e99c (target/arm: Add array for supported PMU
events, generate PMCEID[01]_EL0)
45/48 Checking commit 70a3636dba8d (target/arm: Finish implementation of
PM[X]EVCNTR and PM[X]EVTYPER)
WARNING: Block comments use a leading /* on a separate line
#310: FILE: target/arm/helper.c:1604:
+ /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
WARNING: Block comments use a trailing */ on a separate line
#311: FILE: target/arm/helper.c:1605:
+ * are CONSTRAINED UNPREDICTABLE. */
total: 0 errors, 2 warnings, 406 lines checked
Patch 45/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
46/48 Checking commit 453d2ab0af9e (target/arm: PMU: Add instruction and cycle
events)
WARNING: Block comments use a leading /* on a separate line
#60: FILE: target/arm/helper.c:1047:
+ return use_icount == 1 /* Precise instruction counting */;
total: 0 errors, 1 warnings, 151 lines checked
Patch 46/48 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
47/48 Checking commit f437a7e64815 (target/arm: PMU: Set PMCR.N to 4)
48/48 Checking commit deb04bb05118 (target/arm: Implement PMSWINC)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
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