[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0 |
Date: |
Fri, 1 Feb 2019 16:06:08 +0000 |
Currently the ARMv7M NVIC object's realize method assumes that the
CPU the NVIC is attached to is CPU 0, because it thinks there can
only ever be one CPU in the system. To allow a dual-Cortex-M33
setup we need to remove this assumption; instead the armv7m
wrapper object tells the NVIC its CPU, in the same way that it
already tells the CPU what the NVIC is.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
hw/arm/armv7m.c | 6 ++++--
hw/intc/armv7m_nvic.c | 3 +--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index f4446528307..f9aa83d20ef 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -178,10 +178,12 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
}
}
- /* Tell the CPU where the NVIC is; it will fail realize if it doesn't
- * have one.
+ /*
+ * Tell the CPU where the NVIC is; it will fail realize if it doesn't
+ * have one. Similarly, tell the NVIC where its CPU is.
*/
s->cpu->env.nvic = &s->nvic;
+ s->nvic.cpu = s->cpu;
object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
if (err != NULL) {
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 0beefb05d44..790a3d95849 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2274,8 +2274,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error
**errp)
Error *err = NULL;
int regionlen;
- s->cpu = ARM_CPU(qemu_get_cpu(0));
-
+ /* The armv7m container object will have set our CPU pointer */
if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) {
error_setg(errp, "The NVIC can only be used with a Cortex-M CPU");
return;
--
2.20.1
- [Qemu-devel] [PULL 00/47] target-arm queue, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0,
Peter Maydell <=
- [Qemu-devel] [PULL 01/47] hw/arm/nrf51_soc: set object owner in memory_region_init_ram, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 03/47] armv7m: Make cpu object a child of the armv7m container, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 04/47] armv7m: Pass through start-powered-off CPU property, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 18/47] hw/arm/armsse: Add unimplemented-device stub for cache control registers, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 05/47] hw/arm/iotkit: Rename IoTKit to ARMSSE, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 14/47] hw/arm/armsse: Put each CPU in its own cluster object, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 06/47] hw/arm/iotkit: Refactor into abstract base class and subclass, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 29/47] target/arm/translate-a64: Don't underdecode add/sub extended register, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 22/47] hw/arm/armsse: Add SSE-200 model, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 07/47] hw/arm/iotkit: Rename 'iotkit' local variables and functions, Peter Maydell, 2019/02/01