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[Qemu-devel] [PATCH v3 18/28] target/arm: Implement the access tag cache
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 18/28] target/arm: Implement the access tag cache flushes |
Date: |
Mon, 11 Feb 2019 15:52:48 -0800 |
Like the regular data cache flushes, these are nops within qemu.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f8e4e6f8ae..ed1b258497 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5793,6 +5793,54 @@ static const ARMCPRegInfo mte_reginfo[] = {
{ .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
+ { .name = "IGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "IGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CIGSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGVAP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGVADP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CIGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "IGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "IGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CIGDSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGDVAP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CGDVADP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
+ { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
+ .type = ARM_CP_NOP, .access = PL1_W },
REGINFO_SENTINEL
};
#endif
--
2.17.2
- [Qemu-devel] [PATCH v3 00/28] target/arm: Implement ARMv8.5-MemTag, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 01/28] target/arm: Split out arm_sctlr, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 02/28] target/arm: Split helper_msr_i_pstate into 3, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 03/28] target/arm: Add clear_pstate_bits, share gen_ss_advance, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 04/28] target/arm: Add MTE_ACTIVE to tb_flags, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 05/28] target/arm: Extract TCMA with ARMVAParameters, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 18/28] target/arm: Implement the access tag cache flushes,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 19/28] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 07/28] target/arm: Assert no manual change to CACHED_PSTATE_BITS, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 12/28] target/arm: Implement the GMI instruction, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 15/28] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 06/28] target/arm: Add MTE system registers, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 16/28] target/arm: Implement the STGP instruction, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 17/28] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 09/28] target/arm: Suppress tag check for sp+offset, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 23/28] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 10/28] target/arm: Implement the IRG instruction, Richard Henderson, 2019/02/11