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[Qemu-devel] [PULL 04/27] target/arm: Force result size into dp after op
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/27] target/arm: Force result size into dp after operation |
Date: |
Thu, 14 Feb 2019 19:05:40 +0000 |
From: Richard Henderson <address@hidden>
Rather than a complex set of cases testing for writeback,
adjust DP after performing the operation.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 66cf28c8cbe..eb258958768 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3970,6 +3970,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
tcg_gen_or_i32(tmp, tmp, tmp2);
tcg_temp_free_i32(tmp2);
gen_vfp_msr(tmp);
+ dp = 0; /* always a single precision result */
break;
}
case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */
@@ -3993,20 +3994,25 @@ static int disas_vfp_insn(DisasContext *s, uint32_t
insn)
tcg_gen_or_i32(tmp, tmp, tmp2);
tcg_temp_free_i32(tmp2);
gen_vfp_msr(tmp);
+ dp = 0; /* always a single precision result */
break;
}
case 8: /* cmp */
gen_vfp_cmp(dp);
+ dp = -1; /* no write back */
break;
case 9: /* cmpe */
gen_vfp_cmpe(dp);
+ dp = -1; /* no write back */
break;
case 10: /* cmpz */
gen_vfp_cmp(dp);
+ dp = -1; /* no write back */
break;
case 11: /* cmpez */
gen_vfp_F1_ld0(dp);
gen_vfp_cmpe(dp);
+ dp = -1; /* no write back */
break;
case 12: /* vrintr */
{
@@ -4047,10 +4053,12 @@ static int disas_vfp_insn(DisasContext *s, uint32_t
insn)
break;
}
case 15: /* single<->double conversion */
- if (dp)
+ if (dp) {
gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
- else
+ } else {
gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
+ }
+ dp = !dp; /* result size is opposite */
break;
case 16: /* fuito */
gen_vfp_uito(dp, 0);
@@ -4084,15 +4092,19 @@ static int disas_vfp_insn(DisasContext *s, uint32_t
insn)
break;
case 24: /* ftoui */
gen_vfp_toui(dp, 0);
+ dp = 0; /* always an integer result */
break;
case 25: /* ftouiz */
gen_vfp_touiz(dp, 0);
+ dp = 0; /* always an integer result */
break;
case 26: /* ftosi */
gen_vfp_tosi(dp, 0);
+ dp = 0; /* always an integer result */
break;
case 27: /* ftosiz */
gen_vfp_tosiz(dp, 0);
+ dp = 0; /* always an integer result */
break;
case 28: /* ftosh */
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
@@ -4126,20 +4138,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
return 1;
}
- /* Write back the result. */
- if (op == 15 && (rn >= 8 && rn <= 11)) {
- /* Comparison, do nothing. */
- } else if (op == 15 && dp && ((rn & 0x1c) == 0x18 ||
- (rn & 0x1e) == 0x6)) {
- /* VCVT double to int: always integer result.
- * VCVT double to half precision is always a single
- * precision result.
- */
- gen_mov_vreg_F0(0, rd);
- } else if (op == 15 && rn == 15) {
- /* conversion */
- gen_mov_vreg_F0(!dp, rd);
- } else {
+ /* Write back the result, if any. */
+ if (dp >= 0) {
gen_mov_vreg_F0(dp, rd);
}
--
2.20.1
- [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 01/27] target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 02/27] target/arm: Implement HACR_EL2, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 03/27] target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 04/27] target/arm: Force result size into dp after operation,
Peter Maydell <=
- [Qemu-devel] [PULL 05/27] target/arm: Restructure disas_fp_int_conv, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 06/27] target/arm: relax permission checks for HWCAP_CPUID registers, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 07/27] target/arm: expose CPUID registers to userspace, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 08/27] target/arm: expose MPIDR_EL1 to userspace, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 09/27] target/arm: expose remaining CPUID registers as RAZ, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 10/27] linux-user/elfload: enable HWCAP_CPUID for AArch64, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 12/27] MAINTAINERS: Remove Peter Crosthwaite from various entries, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 15/27] target/arm: Rely on optimization within tcg_gen_gvec_or, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 19/27] target/arm: Remove neon min/max helpers, Peter Maydell, 2019/02/14
- [Qemu-devel] [PULL 14/27] hw/arm/armsse: Fix miswiring of expansion IRQs, Peter Maydell, 2019/02/14