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Re: [Qemu-devel] [PATCH 02/12] target/ppci/mmu: Use LPCR:HR to chose rad
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 02/12] target/ppci/mmu: Use LPCR:HR to chose radix vs. hash translation |
Date: |
Tue, 19 Feb 2019 14:09:48 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Feb 18, 2019 at 10:20:43PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/18/19 7:47 AM, David Gibson wrote:
> > On Fri, Feb 15, 2019 at 06:00:19PM +0100, Cédric Le Goater wrote:
> >> From: Benjamin Herrenschmidt <address@hidden>
> >>
> >> Now that LPCR:HR is set properly for SPAPR, use it for deciding
> >> the translation type, which also works for bare metal
>
> "ppci" -> "ppc" in patch title.
Fixed up inline.
>
> >>
> >> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> >> Signed-off-by: Cédric Le Goater <address@hidden>
> >
> > Reviewed-by: David Gibson <address@hidden>
> >
> >> ---
> >> target/ppc/mmu-book3s-v3.h | 14 +++++++++-----
> >> target/ppc/mmu-book3s-v3.c | 11 ++++++++++-
> >> target/ppc/mmu_helper.c | 9 ++-------
> >> 3 files changed, 21 insertions(+), 13 deletions(-)
> >>
> >> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
> >> index fdf80987d7b2..41b77158622a 100644
> >> --- a/target/ppc/mmu-book3s-v3.h
> >> +++ b/target/ppc/mmu-book3s-v3.h
> >> @@ -43,14 +43,18 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
> >> return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
> >> }
> >>
> >> -static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
> >> +/*
> >> + * The LPCR:HR bit is a shortcut that avoids having to
> >> + * dig out the partition table in the fast path. This is
> >> + * also how the HW uses it.
> >> + */
> >> +static inline bool ppc64_v3_radix(PowerPCCPU *cpu)
> >> {
> >> - PPCVirtualHypervisorClass *vhc =
> >> - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> >> -
> >> - return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> >> + return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR);
> >> }
> >>
> >> +hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr);
> >> +
> >> int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
> >> int mmu_idx);
> >>
> >> diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
> >> index b60df4408f3b..a174e7efc57c 100644
> >> --- a/target/ppc/mmu-book3s-v3.c
> >> +++ b/target/ppc/mmu-book3s-v3.c
> >> @@ -26,9 +26,18 @@
> >> int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
> >> int mmu_idx)
> >> {
> >> - if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
> >> + if (ppc64_v3_radix(cpu)) { /* Guest uses radix */
> >> return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
> >> } else { /* Guest uses hash */
> >> return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
> >> }
> >> }
> >> +
> >> +hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr)
> >> +{
> >> + if (ppc64_v3_radix(cpu)) {
> >> + return ppc_radix64_get_phys_page_debug(cpu, eaddr);
> >> + } else {
> >> + return ppc_hash64_get_phys_page_debug(cpu, eaddr);
> >> + }
> >> +}
> >> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> >> index cefed34da4f2..ae81ee18ae95 100644
> >> --- a/target/ppc/mmu_helper.c
> >> +++ b/target/ppc/mmu_helper.c
> >> @@ -1342,7 +1342,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf,
> >> CPUPPCState *env)
> >> dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> >> break;
> >> case POWERPC_MMU_3_00:
> >> - if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> >> + if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
> >> /* TODO - Unsupported */
> >> } else {
> >> dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> >> @@ -1497,12 +1497,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs,
> >> vaddr addr)
> >> case POWERPC_MMU_2_07:
> >> return ppc_hash64_get_phys_page_debug(cpu, addr);
> >> case POWERPC_MMU_3_00:
> >> - if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> >> - return ppc_radix64_get_phys_page_debug(cpu, addr);
> >> - } else {
> >> - return ppc_hash64_get_phys_page_debug(cpu, addr);
> >> - }
> >> - break;
> >> + return ppc64_v3_get_phys_page_debug(cpu, addr);
> >> #endif
> >>
> >> case POWERPC_MMU_32B:
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-devel] [PATCH 12/12] target/ppc: Basic POWER9 bare-metal radix MMU support, (continued)
- [Qemu-devel] [PATCH 12/12] target/ppc: Basic POWER9 bare-metal radix MMU support, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 03/12] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 09/12] target/ppc: Flush the TLB locally when the LPIDR is written, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 07/12] target/ppc: Add basic support for "new format" HPTE as found on POWER9, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 02/12] target/ppci/mmu: Use LPCR:HR to chose radix vs. hash translation, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 04/12] target/ppc: Fix #include guard in mmu-book3s-v3.h, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 08/12] target/ppc: Fix synchronization of mttcg with broadcast TLB flushes, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 01/12] target/ppc/spapr: Set LPCR:HR when using Radix mode, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 11/12] target/ppc: Support for POWER9 native hash, Cédric Le Goater, 2019/02/15
- [Qemu-devel] [PATCH 10/12] target/ppc: Rename PATB/PATBE -> PATE, Cédric Le Goater, 2019/02/15
- Re: [Qemu-devel] [PATCH 00/12] ppc: add native hash and radix support for POWER9, David Gibson, 2019/02/19