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[Qemu-devel] [PATCH v2 02/11] RISC-V: Replace __builtin_popcount with ct
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v2 02/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC |
Date: |
Thu, 21 Feb 2019 00:43:30 +0000 |
From: Michael Clark <address@hidden>
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_plic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index d12ec3fc9a..b859f919a7 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -383,7 +383,7 @@ static void parse_hart_config(SiFivePLICState *plic)
p = plic->hart_config;
while ((c = *p++)) {
if (c == ',') {
- addrid += __builtin_popcount(modes);
+ addrid += ctpop8(modes);
modes = 0;
hartid++;
} else {
@@ -397,7 +397,7 @@ static void parse_hart_config(SiFivePLICState *plic)
}
}
if (modes) {
- addrid += __builtin_popcount(modes);
+ addrid += ctpop8(modes);
}
hartid++;
--
2.20.1
- [Qemu-devel] [PATCH v2 00/11] Upstream RISC-V fork patches, part 4, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 02/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC,
Alistair Francis <=
- [Qemu-devel] [PATCH v2 01/11] riscv: pmp: Log pmp access errors as guest errors, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 04/11] RISC-V: Remove unnecessary disassembler constraints, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 05/11] elf: Add RISC-V PSABI ELF header defines, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 03/11] RISC-V: Allow interrupt controllers to claim interrupts, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 06/11] RISC-V: linux-user support for RVE ABI, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 07/11] RISC-V: Change local interrupts from edge to level, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 10/11] RISC-V: Update load reservation comment in do_interrupt, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 08/11] RISC-V: Add support for vectored interrupts, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 11/11] riscv: sifive_u: Allow up to 4 CPUs to be created, Alistair Francis, 2019/02/20
- [Qemu-devel] [PATCH v2 09/11] RISC-V: Convert trap debugging to trace events, Alistair Francis, 2019/02/20