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[Qemu-devel] [PATCH v2 5/7] s390x/tcg: Factor out gen_addi_and_wrap_i64(
From: |
David Hildenbrand |
Subject: |
[Qemu-devel] [PATCH v2 5/7] s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address() |
Date: |
Mon, 25 Feb 2019 21:03:16 +0100 |
Also properly wrap in 24bit mode. While at it, convert the comment (and
drop the comment about fundamental TCG optimizations).
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
---
target/s390x/translate.c | 41 +++++++++++++++++++++++++---------------
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 6d36cfed2a..cc52300334 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -382,32 +382,43 @@ static inline void gen_trap(DisasContext *s)
gen_data_exception(0xff);
}
+static void gen_addi_and_wrap_i64(DisasContext *s, TCGv_i64 dst, TCGv_i64 src,
+ int64_t imm)
+{
+ tcg_gen_addi_i64(dst, src, imm);
+ if (!(s->base.tb->flags & FLAG_MASK_64)) {
+ if (s->base.tb->flags & FLAG_MASK_32) {
+ tcg_gen_andi_i64(dst, dst, 0x7fffffff);
+ } else {
+ tcg_gen_andi_i64(dst, dst, 0x00ffffff);
+ }
+ }
+}
+
static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
{
TCGv_i64 tmp = tcg_temp_new_i64();
- bool need_31 = !(s->base.tb->flags & FLAG_MASK_64);
-
- /* Note that d2 is limited to 20 bits, signed. If we crop negative
- displacements early we create larger immedate addends. */
- /* Note that addi optimizes the imm==0 case. */
+ /*
+ * Note that d2 is limited to 20 bits, signed. If we crop negative
+ * displacements early we create larger immedate addends.
+ */
if (b2 && x2) {
tcg_gen_add_i64(tmp, regs[b2], regs[x2]);
- tcg_gen_addi_i64(tmp, tmp, d2);
+ gen_addi_and_wrap_i64(s, tmp, tmp, d2);
} else if (b2) {
- tcg_gen_addi_i64(tmp, regs[b2], d2);
+ gen_addi_and_wrap_i64(s, tmp, regs[b2], d2);
} else if (x2) {
- tcg_gen_addi_i64(tmp, regs[x2], d2);
- } else {
- if (need_31) {
- d2 &= 0x7fffffff;
- need_31 = false;
+ gen_addi_and_wrap_i64(s, tmp, regs[x2], d2);
+ } else if (!(s->base.tb->flags & FLAG_MASK_64)) {
+ if (s->base.tb->flags & FLAG_MASK_32) {
+ tcg_gen_movi_i64(tmp, d2 & 0x7fffffff);
+ } else {
+ tcg_gen_movi_i64(tmp, d2 & 0x00ffffff);
}
+ } else {
tcg_gen_movi_i64(tmp, d2);
}
- if (need_31) {
- tcg_gen_andi_i64(tmp, tmp, 0x7fffffff);
- }
return tmp;
}
--
2.17.2
- [Qemu-devel] [PATCH v2 0/7] s390x/tcg: Cleanups and refactorings for vector instructions, David Hildenbrand, 2019/02/25
- [Qemu-devel] [PATCH v2 1/7] s390x/tcg: RXE has an optional M3 field, David Hildenbrand, 2019/02/25
- [Qemu-devel] [PATCH v2 4/7] s390x/tcg: Factor out vec_full_reg_offset(), David Hildenbrand, 2019/02/25
- [Qemu-devel] [PATCH v2 5/7] s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address(),
David Hildenbrand <=
- [Qemu-devel] [PATCH v2 6/7] s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFP, David Hildenbrand, 2019/02/25
- [Qemu-devel] [PATCH v2 2/7] s390x/tcg: Simplify disassembler operands initialization, David Hildenbrand, 2019/02/25
- [Qemu-devel] [PATCH v2 7/7] s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY, David Hildenbrand, 2019/02/25
- Re: [Qemu-devel] [PATCH v2 0/7] s390x/tcg: Cleanups and refactorings for vector instructions, David Hildenbrand, 2019/02/25
- [Qemu-devel] [PATCH v2 3/7] s390x/tcg: Clarify terminology in vec_reg_offset(), David Hildenbrand, 2019/02/25
- Re: [Qemu-devel] [PATCH v2 0/7] s390x/tcg: Cleanups and refactorings for vector instructions, Cornelia Huck, 2019/02/26