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[Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instructio
From: |
Mateja Marjanovic |
Subject: |
[Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instruction PEXCW |
Date: |
Tue, 26 Feb 2019 13:23:17 +0100 |
From: Mateja Marjanovic <address@hidden>
Add emulation of MMI instruction PEXCW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <address@hidden>
---
target/mips/translate.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 66cea86..7a13841 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24581,6 +24581,75 @@ static void gen_mmi_pexch(DisasContext *ctx)
}
}
+/*
+ * PEXCW rd, rt
+ *
+ * Parallel Exchange Center Word
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXCW | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pexcw(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else if (rt == rd) {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t1, t1, 32);
+
+ tcg_gen_and_i64(cpu_mmr[rd], cpu_mmr[rd], mask1);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
+
+ tcg_gen_and_i64(cpu_gpr[rd], cpu_gpr[rd], mask0);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_or_i64(cpu_mmr[rd], t0, t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t0, t0, 32);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
+ tcg_gen_or_i64(cpu_gpr[rd], t0, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27633,7 +27702,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
- case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
case MMI_OPC_3_PCPYH:
@@ -27645,6 +27713,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_3_PEXCH:
gen_mmi_pexch(ctx);
break;
+ case MMI_OPC_3_PEXCW:
+ gen_mmi_pexcw(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
- [Qemu-devel] [PATCH v2 0/6] target/mips: Add emulation of data communication MMI instructions, Mateja Marjanovic, 2019/02/26
- [Qemu-devel] [PATCH v2 4/6] target/mips: Add emulation of MMI instruction PCPYUD, Mateja Marjanovic, 2019/02/26
- [Qemu-devel] [PATCH v2 3/6] target/mips: Add emulation of MMI instruction PCPYLD, Mateja Marjanovic, 2019/02/26
- [Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instruction PEXCW,
Mateja Marjanovic <=
- [Qemu-devel] [PATCH v2 1/6] target/mips: Preparing for adding MMI instructions, Mateja Marjanovic, 2019/02/26
- [Qemu-devel] [PATCH v2 2/6] target/mips: Add emulation of MMI instruction PCPYH, Mateja Marjanovic, 2019/02/26
- [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH, Mateja Marjanovic, 2019/02/26