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[PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant
From: |
Alistair Francis |
Subject: |
[PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns |
Date: |
Fri, 21 Jan 2022 15:57:51 +1000 |
From: Frank Chang <frank.chang@sifive.com>
All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++++++++++----
1 file changed, 33 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 0bf41aaa1e..e64dddda28 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1908,14 +1908,41 @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
GEN_OPIVX_TRANS(vmax_vx, opivx_check)
/* Vector Single-Width Integer Multiply Instructions */
+
+static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
+{
+ /*
+ * All Zve* extensions support all vector integer instructions,
+ * except that the vmulh integer multiply variants
+ * that return the high word of the product
+ * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
+ * are not included for EEW=64 in Zve64*. (Section 18.2)
+ */
+ return opivv_check(s, a) &&
+ (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
+{
+ /*
+ * All Zve* extensions support all vector integer instructions,
+ * except that the vmulh integer multiply variants
+ * that return the high word of the product
+ * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
+ * are not included for EEW=64 in Zve64*. (Section 18.2)
+ */
+ return opivx_check(s, a) &&
+ (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
-GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check)
+GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check)
+GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check)
GEN_OPIVX_GVEC_TRANS(vmul_vx, muls)
-GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check)
+GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check)
+GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check)
/* Vector Integer Divide Instructions */
GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
--
2.31.1
- [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, (continued)
- [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Alistair Francis, 2022/01/21
- [PULL 12/61] target/riscv: Add host cpu type, Alistair Francis, 2022/01/21
- [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer, Alistair Francis, 2022/01/21
- [PULL 08/61] target/riscv: Implement kvm_arch_put_registers, Alistair Francis, 2022/01/21
- [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing, Alistair Francis, 2022/01/21
- [PULL 15/61] target/riscv: Support virtual time context synchronization, Alistair Francis, 2022/01/21
- [PULL 16/61] target/riscv: enable riscv kvm accel, Alistair Francis, 2022/01/21
- [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers, Alistair Francis, 2022/01/21
- [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment, Alistair Francis, 2022/01/21
- [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, Alistair Francis, 2022/01/21
- [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns,
Alistair Francis <=
- [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, Alistair Francis, 2022/01/21
- [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, Alistair Francis, 2022/01/21
- [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, Alistair Francis, 2022/01/21
- [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, Alistair Francis, 2022/01/21
- [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, Alistair Francis, 2022/01/21
- [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, Alistair Francis, 2022/01/21