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Re: [PULL 53/61] target/riscv: Split out the vill from vtype
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From: |
Alistair Francis |
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Subject: |
Re: [PULL 53/61] target/riscv: Split out the vill from vtype |
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Date: |
Tue, 1 Feb 2022 12:12:23 +1000 |
On Sat, Jan 29, 2022 at 2:10 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Fri, 21 Jan 2022 at 09:42, Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> >
> > From: LIU Zhiwei <zhiwei_liu@c-sky.com>
> >
> > We need not specially process vtype when XLEN changes.
> >
> > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>
> Odd thing I noticed looking at this code: as far as I can see we
> may set env->vill to 1 in the vsetvl helper, but there is nowhere
> that we set it to 0, so once it transitions to 1 it's stuck there
> until the system is reset. Is this really right?
This is really confusing. It implies that you can't set vill from
software, but that just seems to be confusing wording.
Reading
https://lists.riscv.org/g/tech-vector-ext/topic/reliably_set_vtype_vill/86745728
it seems that this is a QEMU bug and the guest should be able to set
the bit as part of vsetvl
@LIU Zhiwei are you able to fix this up?
Alistair
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, (continued)
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, Alistair Francis, 2022/01/21
- [PULL 46/61] target/riscv: Use gdb xml according to max mxlen, Alistair Francis, 2022/01/21
- [PULL 47/61] target/riscv: Relax debug check for pm write, Alistair Francis, 2022/01/21
- [PULL 56/61] target/riscv: Fix check range for first fault only, Alistair Francis, 2022/01/21
- [PULL 57/61] target/riscv: Adjust vector address with mask, Alistair Francis, 2022/01/21
- [PULL 59/61] target/riscv: Set default XLEN for hypervisor, Alistair Francis, 2022/01/21
- [PULL 61/61] target/riscv: Relax UXL field for debugging, Alistair Francis, 2022/01/21
- [PULL 60/61] target/riscv: Enable uxl field write, Alistair Francis, 2022/01/21
- [PULL 53/61] target/riscv: Split out the vill from vtype, Alistair Francis, 2022/01/21
- [PULL 48/61] target/riscv: Adjust csr write mask with XLEN, Alistair Francis, 2022/01/21
- Re: [PULL 00/61] riscv-to-apply queue, Peter Maydell, 2022/01/21