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[PULL 26/54] target/arm: Use tcg_constant for do_coproc_insn
From: |
Peter Maydell |
Subject: |
[PULL 26/54] target/arm: Use tcg_constant for do_coproc_insn |
Date: |
Thu, 28 Apr 2022 15:39:30 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 43 +++++++++++++-----------------------------
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9539d2e8ca2..e4f3db26f66 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4689,8 +4689,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum,
int is64,
* Note that on XScale all cp0..c13 registers do an access check
* call in order to handle c15_cpar.
*/
- TCGv_ptr tmpptr;
- TCGv_i32 tcg_syn, tcg_isread;
uint32_t syndrome;
/* Note that since we are an implementation which takes an
@@ -4733,14 +4731,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum,
int is64,
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
- tmpptr = tcg_const_ptr(ri);
- tcg_syn = tcg_const_i32(syndrome);
- tcg_isread = tcg_const_i32(isread);
- gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn,
- tcg_isread);
- tcg_temp_free_ptr(tmpptr);
- tcg_temp_free_i32(tcg_syn);
- tcg_temp_free_i32(tcg_isread);
+ gen_helper_access_check_cp_reg(cpu_env,
+ tcg_constant_ptr(ri),
+ tcg_constant_i32(syndrome),
+ tcg_constant_i32(isread));
} else if (ri->type & ARM_CP_RAISES_EXC) {
/*
* The readfn or writefn might raise an exception;
@@ -4776,13 +4770,11 @@ static void do_coproc_insn(DisasContext *s, int cpnum,
int is64,
TCGv_i64 tmp64;
TCGv_i32 tmp;
if (ri->type & ARM_CP_CONST) {
- tmp64 = tcg_const_i64(ri->resetvalue);
+ tmp64 = tcg_constant_i64(ri->resetvalue);
} else if (ri->readfn) {
- TCGv_ptr tmpptr;
tmp64 = tcg_temp_new_i64();
- tmpptr = tcg_const_ptr(ri);
- gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
- tcg_temp_free_ptr(tmpptr);
+ gen_helper_get_cp_reg64(tmp64, cpu_env,
+ tcg_constant_ptr(ri));
} else {
tmp64 = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
@@ -4797,13 +4789,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum,
int is64,
} else {
TCGv_i32 tmp;
if (ri->type & ARM_CP_CONST) {
- tmp = tcg_const_i32(ri->resetvalue);
+ tmp = tcg_constant_i32(ri->resetvalue);
} else if (ri->readfn) {
- TCGv_ptr tmpptr;
tmp = tcg_temp_new_i32();
- tmpptr = tcg_const_ptr(ri);
- gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
- tcg_temp_free_ptr(tmpptr);
+ gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri));
} else {
tmp = load_cpu_offset(ri->fieldoffset);
}
@@ -4833,24 +4822,18 @@ static void do_coproc_insn(DisasContext *s, int cpnum,
int is64,
tcg_temp_free_i32(tmplo);
tcg_temp_free_i32(tmphi);
if (ri->writefn) {
- TCGv_ptr tmpptr = tcg_const_ptr(ri);
- gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
- tcg_temp_free_ptr(tmpptr);
+ gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
+ tmp64);
} else {
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
}
tcg_temp_free_i64(tmp64);
} else {
+ TCGv_i32 tmp = load_reg(s, rt);
if (ri->writefn) {
- TCGv_i32 tmp;
- TCGv_ptr tmpptr;
- tmp = load_reg(s, rt);
- tmpptr = tcg_const_ptr(ri);
- gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
- tcg_temp_free_ptr(tmpptr);
+ gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp);
tcg_temp_free_i32(tmp);
} else {
- TCGv_i32 tmp = load_reg(s, rt);
store_cpu_offset(tmp, ri->fieldoffset, 4);
}
}
--
2.25.1
- [PULL 22/54] target/arm: Use tcg_constant for aa32 exceptions, (continued)
- [PULL 22/54] target/arm: Use tcg_constant for aa32 exceptions, Peter Maydell, 2022/04/28
- [PULL 29/54] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32, Peter Maydell, 2022/04/28
- [PULL 17/54] target/arm: Use tcg_constant in disas_fp*, Peter Maydell, 2022/04/28
- [PULL 34/54] target/arm: Use tcg_constant in trans_CPS_v7m, Peter Maydell, 2022/04/28
- [PULL 35/54] target/arm: Use tcg_constant in trans_CSEL, Peter Maydell, 2022/04/28
- [PULL 41/54] target/arm: Use tcg_constant in WHILE, Peter Maydell, 2022/04/28
- [PULL 37/54] target/arm: Use tcg_constant in SINCDEC, INCDEC, Peter Maydell, 2022/04/28
- [PULL 43/54] target/arm: Use tcg_constant in SUBR, Peter Maydell, 2022/04/28
- [PULL 44/54] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm, Peter Maydell, 2022/04/28
- [PULL 52/54] target/arm: Advertise support for FEAT_TTL, Peter Maydell, 2022/04/28
- [PULL 26/54] target/arm: Use tcg_constant for do_coproc_insn,
Peter Maydell <=
- [PULL 39/54] target/arm: Use tcg_constant in {incr, wrap}_last_active, Peter Maydell, 2022/04/28
- [PULL 50/54] hw/arm/smmuv3: Cache event fault record, Peter Maydell, 2022/04/28
- [PULL 53/54] target/arm: Advertise support for FEAT_BBM level 2, Peter Maydell, 2022/04/28
- [PULL 32/54] target/arm: Use tcg_constant in LDM, STM, Peter Maydell, 2022/04/28
- [PULL 27/54] target/arm: Use tcg_constant for gen_srs, Peter Maydell, 2022/04/28
- [PULL 28/54] target/arm: Use tcg_constant for op_s_{rri,rxi}_rot, Peter Maydell, 2022/04/28
- [PULL 30/54] target/arm: Use tcg_constant for v7m MRS, MSR, Peter Maydell, 2022/04/28
- [PULL 33/54] target/arm: Use tcg_constant in CLRM, DLS, WLS, LE, Peter Maydell, 2022/04/28
- [PULL 40/54] target/arm: Use tcg_constant in do_clast_scalar, Peter Maydell, 2022/04/28
- [PULL 45/54] target/arm: Use tcg_constant for predicate descriptors, Peter Maydell, 2022/04/28