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[PATCH v10 12/45] hw/pci/cxl: Create a CXL bus type
From: |
Jonathan Cameron |
Subject: |
[PATCH v10 12/45] hw/pci/cxl: Create a CXL bus type |
Date: |
Fri, 29 Apr 2022 15:40:37 +0100 |
From: Ben Widawsky <ben.widawsky@intel.com>
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the bus to the
correct type. This is less code and useful for debugging via simply
looking at the flags.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/pci-bridge/pci_expander_bridge.c | 9 ++++++++-
include/hw/pci/pci_bus.h | 7 +++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/pci-bridge/pci_expander_bridge.c
b/hw/pci-bridge/pci_expander_bridge.c
index d4514227a8..a6caa1e7b5 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -24,7 +24,7 @@
#include "hw/boards.h"
#include "qom/object.h"
-enum BusType { PCI, PCIE };
+enum BusType { PCI, PCIE, CXL };
#define TYPE_PXB_BUS "pxb-bus"
typedef struct PXBBus PXBBus;
@@ -35,6 +35,10 @@ DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS,
DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS,
TYPE_PXB_PCIE_BUS)
+#define TYPE_PXB_CXL_BUS "pxb-cxl-bus"
+DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS,
+ TYPE_PXB_CXL_BUS)
+
struct PXBBus {
/*< private >*/
PCIBus parent_obj;
@@ -251,6 +255,9 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum
BusType type,
ds = qdev_new(TYPE_PXB_HOST);
if (type == PCIE) {
bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS);
+ } else if (type == CXL) {
+ bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS);
+ bus->flags |= PCI_BUS_CXL;
} else {
bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0,
TYPE_PXB_BUS);
bds = qdev_new("pci-bridge");
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index 347440d42c..eb94e7e85c 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -24,6 +24,8 @@ enum PCIBusFlags {
PCI_BUS_IS_ROOT = 0x0001,
/* PCIe extended configuration space is accessible on this bus */
PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002,
+ /* This is a CXL Type BUS */
+ PCI_BUS_CXL = 0x0004,
};
struct PCIBus {
@@ -53,6 +55,11 @@ struct PCIBus {
Notifier machine_done;
};
+static inline bool pci_bus_is_cxl(PCIBus *bus)
+{
+ return !!(bus->flags & PCI_BUS_CXL);
+}
+
static inline bool pci_bus_is_root(PCIBus *bus)
{
return !!(bus->flags & PCI_BUS_IS_ROOT);
--
2.32.0
- [PATCH v10 02/45] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5), (continued)
- [PATCH v10 02/45] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5), Jonathan Cameron, 2022/04/29
- [PATCH v10 03/45] MAINTAINERS: Add entry for Compute Express Link Emulation, Jonathan Cameron, 2022/04/29
- [PATCH v10 04/45] hw/cxl/device: Introduce a CXL device (8.2.8), Jonathan Cameron, 2022/04/29
- [PATCH v10 05/45] hw/cxl/device: Implement the CAP array (8.2.8.1-2), Jonathan Cameron, 2022/04/29
- [PATCH v10 06/45] hw/cxl/device: Implement basic mailbox (8.2.8.4), Jonathan Cameron, 2022/04/29
- [PATCH v10 07/45] hw/cxl/device: Add memory device utilities, Jonathan Cameron, 2022/04/29
- [PATCH v10 08/45] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1), Jonathan Cameron, 2022/04/29
- [PATCH v10 09/45] hw/cxl/device: Timestamp implementation (8.2.9.3), Jonathan Cameron, 2022/04/29
- [PATCH v10 10/45] hw/cxl/device: Add log commands (8.2.9.4) + CEL, Jonathan Cameron, 2022/04/29
- [PATCH v10 11/45] hw/pxb: Use a type for realizing expanders, Jonathan Cameron, 2022/04/29
- [PATCH v10 12/45] hw/pci/cxl: Create a CXL bus type,
Jonathan Cameron <=
- [PATCH v10 13/45] cxl: Machine level control on whether CXL support is enabled, Jonathan Cameron, 2022/04/29
- [PATCH v10 14/45] hw/pxb: Allow creation of a CXL PXB (host bridge), Jonathan Cameron, 2022/04/29
- [PATCH v10 15/45] qtest/cxl: Introduce initial test for pxb-cxl only., Jonathan Cameron, 2022/04/29
- [PATCH v10 16/45] hw/cxl/rp: Add a root port, Jonathan Cameron, 2022/04/29
- [PATCH v10 17/45] hw/cxl/device: Add a memory device (8.2.8.5), Jonathan Cameron, 2022/04/29
- [PATCH v10 18/45] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Jonathan Cameron, 2022/04/29
- [PATCH v10 19/45] hw/cxl/device: Add some trivial commands, Jonathan Cameron, 2022/04/29
- [PATCH v10 20/45] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Jonathan Cameron, 2022/04/29
- [PATCH v10 21/45] hw/cxl/device: Implement get/set Label Storage Area (LSA), Jonathan Cameron, 2022/04/29
- [PATCH v10 22/45] qtests/cxl: Add initial root port and CXL type3 tests, Jonathan Cameron, 2022/04/29