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[PULL 16/23] target/riscv: Fix typo of mimpid cpu option
From: |
Alistair Francis |
Subject: |
[PULL 16/23] target/riscv: Fix typo of mimpid cpu option |
Date: |
Wed, 25 May 2022 08:44:21 +1000 |
From: Frank Chang <frank.chang@sifive.com>
"mimpid" cpu option was mistyped to "mipid".
Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid
CSR values")
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220523153147.15371-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 4 ++--
target/riscv/csr.c | 8 ++++----
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f5ff7294c6..44975e3e5a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -408,7 +408,7 @@ struct RISCVCPUConfig {
uint32_t mvendorid;
uint64_t marchid;
- uint64_t mipid;
+ uint64_t mimpid;
/* Vendor-specific custom extensions */
bool ext_XVentanaCondOps;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 87e1eddce6..fe8ceb4133 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -37,7 +37,7 @@
#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
(QEMU_VERSION_MINOR << 8) | \
(QEMU_VERSION_MICRO))
-#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
+#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
@@ -869,7 +869,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
- DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+ DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4ea7df02c9..0d5bc2f41d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -674,13 +674,13 @@ static RISCVException read_marchid(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException read_mipid(CPURISCVState *env, int csrno,
- target_ulong *val)
+static RISCVException read_mimpid(CPURISCVState *env, int csrno,
+ target_ulong *val)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
- *val = cpu->cfg.mipid;
+ *val = cpu->cfg.mimpid;
return RISCV_EXCP_NONE;
}
@@ -3372,7 +3372,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Machine Information Registers */
[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
[CSR_MARCHID] = { "marchid", any, read_marchid },
- [CSR_MIMPID] = { "mimpid", any, read_mipid },
+ [CSR_MIMPID] = { "mimpid", any, read_mimpid },
[CSR_MHARTID] = { "mhartid", any, read_mhartid },
[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
--
2.35.3
- [PULL 05/23] target/riscv: Add short-isa-string option, (continued)
- [PULL 05/23] target/riscv: Add short-isa-string option, Alistair Francis, 2022/05/24
- [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike), Alistair Francis, 2022/05/24
- [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan), Alistair Francis, 2022/05/24
- [PULL 08/23] target/riscv: Fix coding style on "G" expansion, Alistair Francis, 2022/05/24
- [PULL 09/23] target/riscv: Disable "G" by default, Alistair Francis, 2022/05/24
- [PULL 10/23] target/riscv: Change "G" expansion, Alistair Francis, 2022/05/24
- [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters, Alistair Francis, 2022/05/24
- [PULL 12/23] target/riscv: Move/refactor ISA extension checks, Alistair Francis, 2022/05/24
- [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors, Alistair Francis, 2022/05/24
- [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize, Alistair Francis, 2022/05/24
- [PULL 16/23] target/riscv: Fix typo of mimpid cpu option,
Alistair Francis <=
- [PULL 17/23] target/riscv: Fix csr number based privilege checking, Alistair Francis, 2022/05/24
- [PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode, Alistair Francis, 2022/05/24
- [PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps, Alistair Francis, 2022/05/24
- [PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices, Alistair Francis, 2022/05/24
- [PULL 21/23] target/riscv: add zicsr/zifencei to isa_string, Alistair Francis, 2022/05/24
- [PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01, Alistair Francis, 2022/05/24
- [PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage, Alistair Francis, 2022/05/24
- [PULL 11/23] target/riscv: FP extension requirements, Alistair Francis, 2022/05/24
- Re: [PULL 00/23] riscv-to-apply queue, Richard Henderson, 2022/05/24