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[PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_in
From: |
Richard Henderson |
Subject: |
[PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_insn |
Date: |
Sat, 1 Oct 2022 09:22:42 -0700 |
Remove the use of regime_is_secure from v7m_read_half_insn, using
the new parameter instead.
As it happens, both callers pass true, propagated from the argument
to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument,
but that is a detail of v7m_handle_execute_nsc we need not expose
to the callee.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/m_helper.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 5ee4ee15b3..203ba411f6 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -1981,7 +1981,7 @@ static bool do_v7m_function_return(ARMCPU *cpu)
return true;
}
-static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
+static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
uint32_t addr, uint16_t *insn)
{
/*
@@ -2003,8 +2003,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx
mmu_idx,
ARMMMUFaultInfo fi = {};
MemTxResult txres;
- v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
- regime_is_secure(env, mmu_idx), &sattrs);
+ v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattrs);
if (!sattrs.nsc || sattrs.ns) {
/*
* This must be the second half of the insn, and it straddles a
@@ -2109,7 +2108,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
/* We want to do the MPU lookup as secure; work out what mmu_idx that is */
mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
- if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
+ if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) {
return false;
}
@@ -2125,7 +2124,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
goto gen_invep;
}
- if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
+ if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn)) {
return false;
}
--
2.34.1
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, (continued)
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Peter Maydell, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Richard Henderson, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Peter Maydell, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Richard Henderson, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Peter Maydell, 2022/10/07
[PATCH v3 02/42] target/arm: Add is_secure parameter to get_phys_addr_lpae, Richard Henderson, 2022/10/01
[PATCH v3 03/42] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/10/01
[PATCH v3 04/42] target/arm: Add is_secure parameter to regime_translation_disabled, Richard Henderson, 2022/10/01
[PATCH v3 05/42] target/arm: Split out get_phys_addr_with_secure, Richard Henderson, 2022/10/01
[PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_insn,
Richard Henderson <=
[PATCH v3 07/42] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/10/01
[PATCH v3 08/42] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/10/01
[PATCH v3 13/42] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/10/01
[PATCH v3 10/42] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/10/01
[PATCH v3 16/42] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/10/01
[PATCH v3 17/42] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/10/01
[PATCH v3 18/42] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/10/01
[PATCH v3 12/42] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/10/01
[PATCH v3 14/42] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/10/01
[PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled, Richard Henderson, 2022/10/01