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[PULL 41/53] target/i386: clarify (un)signedness of immediates from 0F3A
From: |
Paolo Bonzini |
Subject: |
[PULL 41/53] target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes |
Date: |
Tue, 18 Oct 2022 15:30:30 +0200 |
Three-byte opcodes from the 0F3Ah area all have an immediate byte which
is usually unsigned. Clarify in the helper code that it is unsigned;
the new decoder treats immediates as signed by default, and seeing
an intN_t in the prototype might give the wrong impression that one
can use decode->immediate directly.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/ops_sse.h | 8 ++++----
target/i386/ops_sse_header.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 090ba013b3..e7830ff277 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -1605,17 +1605,17 @@ SSE_HELPER_W(helper_psignw, FSIGNW)
SSE_HELPER_L(helper_psignd, FSIGNL)
void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s,
- int32_t shift)
+ uint32_t imm)
{
int i;
/* XXX could be checked during translation */
- if (shift >= (SHIFT ? 32 : 16)) {
+ if (imm >= (SHIFT ? 32 : 16)) {
for (i = 0; i < (1 << SHIFT); i++) {
d->Q(i) = 0;
}
} else {
- shift <<= 3;
+ int shift = imm * 8;
#define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0)
#if SHIFT == 0
d->Q(0) = SHR(s->Q(0), shift - 0) |
@@ -2093,7 +2093,7 @@ static inline int pcmp_val(Reg *r, uint8_t ctrl, int i)
}
static inline unsigned pcmpxstrx(CPUX86State *env, Reg *d, Reg *s,
- int8_t ctrl, int valids, int validd)
+ uint8_t ctrl, int valids, int validd)
{
unsigned int res = 0;
int v;
diff --git a/target/i386/ops_sse_header.h b/target/i386/ops_sse_header.h
index 440f1c0e78..98178be148 100644
--- a/target/i386/ops_sse_header.h
+++ b/target/i386/ops_sse_header.h
@@ -335,7 +335,7 @@ DEF_HELPER_4(glue(pshufb, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignb, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignd, SUFFIX), void, env, Reg, Reg, Reg)
-DEF_HELPER_5(glue(palignr, SUFFIX), void, env, Reg, Reg, Reg, s32)
+DEF_HELPER_5(glue(palignr, SUFFIX), void, env, Reg, Reg, Reg, i32)
/* SSE4.1 op helpers */
#if SHIFT >= 1
--
2.37.3
- [PULL 18/53] target/i386: Define XMMReg and access macros, align ZMM registers, (continued)
- [PULL 18/53] target/i386: Define XMMReg and access macros, align ZMM registers, Paolo Bonzini, 2022/10/18
- [PULL 19/53] target/i386: make ldo/sto operations consistent with ldq, Paolo Bonzini, 2022/10/18
- [PULL 21/53] target/i386: add core of new i386 decoder, Paolo Bonzini, 2022/10/18
- [PULL 22/53] target/i386: add ALU load/writeback core, Paolo Bonzini, 2022/10/18
- [PULL 38/53] target/i386: reimplement 0x0f 0x78-0x7f, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 31/53] target/i386: support operand merging in binary scalar helpers, Paolo Bonzini, 2022/10/18
- [PULL 39/53] target/i386: reimplement 0x0f 0x70-0x77, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 34/53] target/i386: Introduce 256-bit vector helpers, Paolo Bonzini, 2022/10/18
- [PULL 25/53] target/i386: add AVX_EN hflag, Paolo Bonzini, 2022/10/18
- [PULL 24/53] target/i386: add CPUID feature checks to new decoder, Paolo Bonzini, 2022/10/18
- [PULL 41/53] target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes,
Paolo Bonzini <=
- [PULL 28/53] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder, Paolo Bonzini, 2022/10/18
- [PULL 40/53] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 32/53] target/i386: provide 3-operand versions of unary scalar helpers, Paolo Bonzini, 2022/10/18
- [PULL 43/53] target/i386: Use tcg gvec ops for pmovmskb, Paolo Bonzini, 2022/10/18
- [PULL 36/53] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 35/53] target/i386: reimplement 0x0f 0x60-0x6f, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 23/53] target/i386: add CPUID[EAX=7,ECX=0].ECX to DisasContext, Paolo Bonzini, 2022/10/18
- [PULL 44/53] target/i386: reimplement 0x0f 0x38, add AVX, Paolo Bonzini, 2022/10/18
- [PULL 53/53] target/i386: remove old SSE decoder, Paolo Bonzini, 2022/10/18
- [PULL 27/53] target/i386: validate SSE prefixes directly in the decoding table, Paolo Bonzini, 2022/10/18