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[PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg()
From: |
Alistair Francis |
Subject: |
[PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() |
Date: |
Fri, 5 May 2023 11:02:01 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This function was created to move the sync between cpu->cfg.ext_N bit
changes to env->misa_ext* from the validation step to an ealier step,
giving us a guarantee that we could use either cpu->cfg.ext_N or
riscv_has_ext(env,N) in the validation.
We don't have any cpu->cfg.ext_N left that has an existing MISA bit
(cfg.ext_g will be handled shortly). The function is now a no-op, simply
copying the existing values of misa_ext* back to misa_ext*.
Remove it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 52 ----------------------------------------------
1 file changed, 52 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 13ff37250e..1ecb82bb5d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1141,50 +1141,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu,
Error **errp)
#endif
}
-static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
-{
- uint32_t ext = 0;
-
- if (riscv_has_ext(env, RVI)) {
- ext |= RVI;
- }
- if (riscv_has_ext(env, RVE)) {
- ext |= RVE;
- }
- if (riscv_has_ext(env, RVM)) {
- ext |= RVM;
- }
- if (riscv_has_ext(env, RVA)) {
- ext |= RVA;
- }
- if (riscv_has_ext(env, RVF)) {
- ext |= RVF;
- }
- if (riscv_has_ext(env, RVD)) {
- ext |= RVD;
- }
- if (riscv_has_ext(env, RVC)) {
- ext |= RVC;
- }
- if (riscv_has_ext(env, RVS)) {
- ext |= RVS;
- }
- if (riscv_has_ext(env, RVU)) {
- ext |= RVU;
- }
- if (riscv_has_ext(env, RVH)) {
- ext |= RVH;
- }
- if (riscv_has_ext(env, RVV)) {
- ext |= RVV;
- }
- if (riscv_has_ext(env, RVJ)) {
- ext |= RVJ;
- }
-
- env->misa_ext = env->misa_ext_mask = ext;
-}
-
static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
{
if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
@@ -1228,14 +1184,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
set_priv_version(env, priv_version);
}
- /*
- * We can't be sure of whether we set defaults during cpu_init()
- * or whether the user enabled/disabled some bits via cpu->cfg
- * flags. Sync env->misa_ext with cpu->cfg now to allow us to
- * use just env->misa_ext later.
- */
- riscv_cpu_sync_misa_cfg(env);
-
riscv_cpu_validate_misa_priv(env, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
--
2.40.0
- [PULL 37/89] target/riscv: remove cpu->cfg.ext_a, (continued)
- [PULL 37/89] target/riscv: remove cpu->cfg.ext_a, Alistair Francis, 2023/05/04
- [PULL 42/89] target/riscv: remove cpu->cfg.ext_e, Alistair Francis, 2023/05/04
- Re: [PULL 00/89] riscv-to-apply queue, Alistair Francis, 2023/05/04
- [PULL 43/89] target/riscv: remove cpu->cfg.ext_m, Alistair Francis, 2023/05/04
- [PULL 41/89] target/riscv: remove cpu->cfg.ext_i, Alistair Francis, 2023/05/04
- [PULL 45/89] target/riscv: remove cpu->cfg.ext_u, Alistair Francis, 2023/05/04
- [PULL 44/89] target/riscv: remove cpu->cfg.ext_s, Alistair Francis, 2023/05/04
- [PULL 46/89] target/riscv: remove cpu->cfg.ext_h, Alistair Francis, 2023/05/04
- [PULL 48/89] target/riscv: remove cpu->cfg.ext_v, Alistair Francis, 2023/05/04
- [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg(),
Alistair Francis <=
- [PULL 47/89] target/riscv: remove cpu->cfg.ext_j, Alistair Francis, 2023/05/04
- [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g, Alistair Francis, 2023/05/04
- [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props(), Alistair Francis, 2023/05/04
- [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Alistair Francis, 2023/05/04
- [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET, Alistair Francis, 2023/05/04
- [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H, Alistair Francis, 2023/05/04
- [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus, Alistair Francis, 2023/05/04
- [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx, Alistair Francis, 2023/05/04
- [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags, Alistair Francis, 2023/05/04
- [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Alistair Francis, 2023/05/04