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[PATCH v5 42/54] tcg/arm: Use atom_and_align_for_opc
From: |
Richard Henderson |
Subject: |
[PATCH v5 42/54] tcg/arm: Use atom_and_align_for_opc |
Date: |
Mon, 15 May 2023 07:33:01 -0700 |
No change to the ultimate load/store routines yet, so some atomicity
conditions not yet honored, but plumbs the change to alignment through
the relevant functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index e5aed03247..add8cc1fd5 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1323,6 +1323,7 @@ typedef struct {
TCGReg base;
int index;
bool index_scratch;
+ TCGAtomAlign aa;
} HostAddress;
bool tcg_target_has_memory_bswap(MemOp memop)
@@ -1379,8 +1380,26 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext
*s, HostAddress *h,
{
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
- MemOp a_bits = get_alignment_bits(opc);
- unsigned a_mask = (1 << a_bits) - 1;
+ unsigned a_mask;
+
+#ifdef CONFIG_SOFTMMU
+ *h = (HostAddress){
+ .cond = COND_AL,
+ .base = addrlo,
+ .index = TCG_REG_R1,
+ .index_scratch = true,
+ };
+#else
+ *h = (HostAddress){
+ .cond = COND_AL,
+ .base = addrlo,
+ .index = guest_base ? TCG_REG_GUEST_BASE : -1,
+ .index_scratch = false,
+ };
+#endif
+
+ h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
+ a_mask = (1 << h->aa.align) - 1;
#ifdef CONFIG_SOFTMMU
int mem_index = get_mmuidx(oi);
@@ -1469,13 +1488,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext
*s, HostAddress *h,
if (TARGET_LONG_BITS == 64) {
tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
}
-
- *h = (HostAddress){
- .cond = COND_AL,
- .base = addrlo,
- .index = TCG_REG_R1,
- .index_scratch = true,
- };
#else
if (a_mask) {
ldst = new_ldst_label(s);
@@ -1484,18 +1496,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext
*s, HostAddress *h,
ldst->addrlo_reg = addrlo;
ldst->addrhi_reg = addrhi;
- /* We are expecting a_bits to max out at 7 */
+ /* We are expecting alignment to max out at 7 */
tcg_debug_assert(a_mask <= 0xff);
/* tst addr, #mask */
tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
}
-
- *h = (HostAddress){
- .cond = COND_AL,
- .base = addrlo,
- .index = guest_base ? TCG_REG_GUEST_BASE : -1,
- .index_scratch = false,
- };
#endif
return ldst;
--
2.34.1
- [PATCH v5 27/54] tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32, (continued)
- [PATCH v5 27/54] tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32, Richard Henderson, 2023/05/15
- [PATCH v5 25/54] tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13, Richard Henderson, 2023/05/15
- [PATCH v5 32/54] tcg/loongarch64: Support softmmu unaligned accesses, Richard Henderson, 2023/05/15
- [PATCH v5 29/54] tcg/sparc64: Use standard slow path for softmmu, Richard Henderson, 2023/05/15
- [PATCH v5 37/54] tcg: Merge tcg_out_helper_load_regs into caller, Richard Henderson, 2023/05/15
- [PATCH v5 41/54] tcg/aarch64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 42/54] tcg/arm: Use atom_and_align_for_opc,
Richard Henderson <=
- [PATCH v5 40/54] tcg/i386: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 48/54] tcg/sparc64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 43/54] tcg/loongarch64: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 44/54] tcg/mips: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 50/54] tcg/i386: Support 128-bit load/store with have_atomic16, Richard Henderson, 2023/05/15
- [PATCH v5 47/54] tcg/s390x: Use atom_and_align_for_opc, Richard Henderson, 2023/05/15
- [PATCH v5 49/54] tcg/i386: Honor 64-bit atomicity in 32-bit mode, Richard Henderson, 2023/05/15
- [PATCH v5 52/54] tcg/aarch64: Support 128-bit load/store, Richard Henderson, 2023/05/15