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Re: [PATCH RFC 1/5] hw/cxl: Use define for build bug detection
From: |
Ira Weiny |
Subject: |
Re: [PATCH RFC 1/5] hw/cxl: Use define for build bug detection |
Date: |
Thu, 18 May 2023 13:19:12 -0700 |
Jonathan Cameron wrote:
> On Wed, 17 May 2023 19:45:54 -0700
> Ira Weiny <ira.weiny@intel.com> wrote:
>
> > Magic numbers can be confusing.
> >
> > Use the range size define for CXL.cachemem rather than a magic number.
> > Update/add spec references.
> >
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
>
> I guess we should do a scrub to move all refs to 3.0 soon
> given it's horrible having a mixture of spec versions for the references.
>
> For future specs, we should only do this when sufficient X.Y references
> have started to appear - I think that's true for r3.0 now.
For the kernel side I think Dan is taking the 'if you are updating it then
update the spec' but otherwise leave it be. So since I'm touching the
code I updated it.
I agree, it is a pain to have to look at the 2.0 spec but you can do it.
Ira
[PATCH RFC 2/5] hw/cxl: Refactor component register initialization, Ira Weiny, 2023/05/17
[PATCH RFC 3/5] hw/cxl: Derive a CXL accelerator device from Type-3, Ira Weiny, 2023/05/17
[PATCH RFC 5/5] hw/cxl: Add UIO HDM decoder register fields, Ira Weiny, 2023/05/17
[PATCH RFC 4/5] hw/cxl/accel: Add Back-Invalidate decoder capbility structure, Ira Weiny, 2023/05/17