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[PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions
From: |
Weiwei Li |
Subject: |
[PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions |
Date: |
Tue, 23 May 2023 17:35:36 +0800 |
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
disas/riscv.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 49a3eb6ac4..108bc2127d 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4592,16 +4592,24 @@ static void format_inst(char *buf, size_t buflen,
size_t tab, rv_decode *dec)
append(buf, rv_ireg_name_sym[dec->rs2], buflen);
break;
case '3':
- append(buf, rv_freg_name_sym[dec->rd], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] :
+ rv_freg_name_sym[dec->rd],
+ buflen);
break;
case '4':
- append(buf, rv_freg_name_sym[dec->rs1], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] :
+ rv_freg_name_sym[dec->rs1],
+ buflen);
break;
case '5':
- append(buf, rv_freg_name_sym[dec->rs2], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] :
+ rv_freg_name_sym[dec->rs2],
+ buflen);
break;
case '6':
- append(buf, rv_freg_name_sym[dec->rs3], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] :
+ rv_freg_name_sym[dec->rs3],
+ buflen);
break;
case '7':
snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
--
2.25.1
- [PATCH v2 0/8] Add support for extension specific disas, Weiwei Li, 2023/05/23
- [PATCH v2 4/8] disas/riscv.c: Support disas for Zcm* extensions, Weiwei Li, 2023/05/23
- [PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions,
Weiwei Li <=
- [PATCH v2 2/8] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h, Weiwei Li, 2023/05/23
- [PATCH v2 1/8] disas: Change type of disassemble_info.target_info to pointer, Weiwei Li, 2023/05/23
- [PATCH v2 3/8] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info, Weiwei Li, 2023/05/23
- [PATCH v2 8/8] disas/riscv.c: Remove redundant parentheses, Weiwei Li, 2023/05/23