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[PULL 10/23] tcg/mips: Try three insns with shift and add in tcg_out_mov
From: |
Richard Henderson |
Subject: |
[PULL 10/23] tcg/mips: Try three insns with shift and add in tcg_out_movi |
Date: |
Thu, 25 May 2023 11:10:23 -0700 |
These sequences are inexpensive to test. Maxing out at three insns
results in the same space as a load plus the constant pool entry.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 44 +++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 9fab424ecc..b86a0679af 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -569,6 +569,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type,
TCGReg ret,
tcg_target_long arg, TCGReg tbreg)
{
tcg_target_long tmp;
+ int sh, lo;
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
arg = (int32_t)arg;
@@ -591,6 +592,49 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type,
TCGReg ret,
return;
}
+ /*
+ * Load bitmasks with a right-shift. This is good for things
+ * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4.
+ * or similarly using LUI. For this to work, bit 31 must be set.
+ */
+ if (arg > 0 && (int32_t)arg < 0) {
+ sh = clz64(arg);
+ if (tcg_out_movi_one(s, ret, arg << sh)) {
+ tcg_out_dsrl(s, ret, ret, sh);
+ return;
+ }
+ }
+
+ /*
+ * Load slightly larger constants using left-shift.
+ * Limit this sequence to 3 insns to avoid too much expansion.
+ */
+ sh = ctz64(arg);
+ if (sh && tcg_out_movi_two(s, ret, arg >> sh)) {
+ tcg_out_dsll(s, ret, ret, sh);
+ return;
+ }
+
+ /*
+ * Load slightly larger constants using left-shift and add/or.
+ * Prefer addi with a negative immediate when that would produce
+ * a larger shift. For this to work, bits 15 and 16 must be set.
+ */
+ lo = arg & 0xffff;
+ if (lo) {
+ if ((arg & 0x18000) == 0x18000) {
+ lo = (int16_t)arg;
+ }
+ tmp = arg - lo;
+ sh = ctz64(tmp);
+ tmp >>= sh;
+ if (tcg_out_movi_one(s, ret, tmp)) {
+ tcg_out_dsll(s, ret, ret, sh);
+ tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo);
+ return;
+ }
+ }
+
/* Otherwise, put 64-bit constants into the constant pool. */
tcg_out_movi_pool(s, ret, arg, tbreg);
}
--
2.34.1
- [PULL 00/23] tcg patch queue, Richard Henderson, 2023/05/25
- [PULL 01/23] tcg/mips: Move TCG_AREG0 to S8, Richard Henderson, 2023/05/25
- [PULL 03/23] tcg/mips: Unify TCG_GUEST_BASE_REG tests, Richard Henderson, 2023/05/25
- [PULL 02/23] tcg/mips: Move TCG_GUEST_BASE_REG to S7, Richard Henderson, 2023/05/25
- [PULL 04/23] tcg/mips: Create and use TCG_REG_TB, Richard Henderson, 2023/05/25
- [PULL 06/23] tcg/mips: Split out tcg_out_movi_two, Richard Henderson, 2023/05/25
- [PULL 05/23] tcg/mips: Split out tcg_out_movi_one, Richard Henderson, 2023/05/25
- [PULL 07/23] tcg/mips: Use the constant pool for 64-bit constants, Richard Henderson, 2023/05/25
- [PULL 08/23] tcg/mips: Aggressively use the constant pool for n64 calls, Richard Henderson, 2023/05/25
- [PULL 09/23] tcg/mips: Try tb-relative addresses in tcg_out_movi, Richard Henderson, 2023/05/25
- [PULL 10/23] tcg/mips: Try three insns with shift and add in tcg_out_movi,
Richard Henderson <=
- [PULL 11/23] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF, Richard Henderson, 2023/05/25
- [PULL 12/23] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN, Richard Henderson, 2023/05/25
- [PULL 13/23] disas/riscv: Decode czero.{eqz,nez}, Richard Henderson, 2023/05/25
- [PULL 15/23] tcg/riscv: Support ANDN, ORN, XNOR from Zbb, Richard Henderson, 2023/05/25
- [PULL 14/23] tcg/riscv: Probe for Zba, Zbb, Zicond extensions, Richard Henderson, 2023/05/25
- [PULL 16/23] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb, Richard Henderson, 2023/05/25
- [PULL 17/23] tcg/riscv: Use ADD.UW for guest address generation, Richard Henderson, 2023/05/25
- [PULL 18/23] tcg/riscv: Support rotates from Zbb, Richard Henderson, 2023/05/25
- [PULL 20/23] tcg/riscv: Support CPOP from Zbb, Richard Henderson, 2023/05/25
- [PULL 21/23] tcg/riscv: Improve setcond expansion, Richard Henderson, 2023/05/25