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[PULL 16/27] accel/tcg: Add aarch64 store_atom_insert_al16
From: |
Richard Henderson |
Subject: |
[PULL 16/27] accel/tcg: Add aarch64 store_atom_insert_al16 |
Date: |
Tue, 30 May 2023 11:59:38 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
host/include/aarch64/host/store-insert-al16.h | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 host/include/aarch64/host/store-insert-al16.h
diff --git a/host/include/aarch64/host/store-insert-al16.h
b/host/include/aarch64/host/store-insert-al16.h
new file mode 100644
index 0000000000..1943155bc6
--- /dev/null
+++ b/host/include/aarch64/host/store-insert-al16.h
@@ -0,0 +1,47 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Atomic store insert into 128-bit, AArch64 version.
+ *
+ * Copyright (C) 2023 Linaro, Ltd.
+ */
+
+#ifndef AARCH64_STORE_INSERT_AL16_H
+#define AARCH64_STORE_INSERT_AL16_H
+
+/**
+ * store_atom_insert_al16:
+ * @p: host address
+ * @val: shifted value to store
+ * @msk: mask for value to store
+ *
+ * Atomically store @val to @p masked by @msk.
+ */
+static inline void ATTRIBUTE_ATOMIC128_OPT
+store_atom_insert_al16(Int128 *ps, Int128 val, Int128 msk)
+{
+ /*
+ * GCC only implements __sync* primitives for int128 on aarch64.
+ * We can do better without the barriers, and integrating the
+ * arithmetic into the load-exclusive/store-conditional pair.
+ */
+ uint64_t tl, th, vl, vh, ml, mh;
+ uint32_t fail;
+
+ qemu_build_assert(!HOST_BIG_ENDIAN);
+ vl = int128_getlo(val);
+ vh = int128_gethi(val);
+ ml = int128_getlo(msk);
+ mh = int128_gethi(msk);
+
+ asm("0: ldxp %[l], %[h], %[mem]\n\t"
+ "bic %[l], %[l], %[ml]\n\t"
+ "bic %[h], %[h], %[mh]\n\t"
+ "orr %[l], %[l], %[vl]\n\t"
+ "orr %[h], %[h], %[vh]\n\t"
+ "stxp %w[f], %[l], %[h], %[mem]\n\t"
+ "cbnz %w[f], 0b\n"
+ : [mem] "+Q"(*ps), [f] "=&r"(fail), [l] "=&r"(tl), [h] "=&r"(th)
+ : [vl] "r"(vl), [vh] "r"(vh), [ml] "r"(ml), [mh] "r"(mh));
+}
+
+#endif /* AARCH64_STORE_INSERT_AL16_H */
--
2.34.1
- [PULL 15/27] accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8, (continued)
- [PULL 15/27] accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8, Richard Henderson, 2023/05/30
- [PULL 19/27] decodetree: Fix recursion in prop_format and build_tree, Richard Henderson, 2023/05/30
- [PULL 27/27] tests/decode: Add tests for various named-field cases, Richard Henderson, 2023/05/30
- [PULL 26/27] scripts/decodetree: Implement named field support, Richard Henderson, 2023/05/30
- [PULL 05/27] tcg/i386: Support 128-bit load/store, Richard Henderson, 2023/05/30
- [PULL 09/27] tcg/aarch64: Support 128-bit load/store, Richard Henderson, 2023/05/30
- [PULL 11/27] tcg/s390x: Support 128-bit load/store, Richard Henderson, 2023/05/30
- [PULL 10/27] tcg/ppc: Support 128-bit load/store, Richard Henderson, 2023/05/30
- [PULL 08/27] tcg/aarch64: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/05/30
- [PULL 07/27] tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2, Richard Henderson, 2023/05/30
- [PULL 16/27] accel/tcg: Add aarch64 store_atom_insert_al16,
Richard Henderson <=
- [PULL 12/27] accel/tcg: Extract load_atom_extract_al16_or_al8 to host header, Richard Henderson, 2023/05/30
- [PULL 20/27] decodetree: Diagnose empty pattern group, Richard Henderson, 2023/05/30
- [PULL 23/27] docs: Document decodetree named field syntax, Richard Henderson, 2023/05/30
- [PULL 25/27] scripts/decodetree: Implement a topological sort, Richard Henderson, 2023/05/30
- Re: [PULL 00/27] tcg patch queue, Richard Henderson, 2023/05/30