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[PULL 30/54] target/riscv: Set the correct exception for implict G-stage
From: |
Alistair Francis |
Subject: |
[PULL 30/54] target/riscv: Set the correct exception for implict G-stage translation fail |
Date: |
Mon, 10 Jul 2023 22:31:41 +1000 |
From: Jason Chien <jason.chien@sifive.com>
The privileged spec states:
For a memory access made to support VS-stage address translation (such as
to read/write a VS-level page table), permissions are checked as though
for a load or store, not for the original access type. However, any
exception is always reported for the original access type (instruction,
load, or store/AMO).
The current implementation converts the access type to LOAD if implicit
G-stage translation fails which results in only reporting "Load guest-page
fault". This commit removes the convertion of access type, so the reported
exception conforms to the spec.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230627074915.7686-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bb9d923818..9f611d89bb 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1282,7 +1282,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
if (ret == TRANSLATE_G_STAGE_FAIL) {
first_stage_error = false;
two_stage_indirect_error = true;
- access_type = MMU_DATA_LOAD;
}
qemu_log_mask(CPU_LOG_MMU,
--
2.40.1
- [PULL 20/54] target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson, (continued)
- [PULL 20/54] target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson, Alistair Francis, 2023/07/10
- [PULL 21/54] target/riscv: Only build KVM guest with same wordsize as host, Alistair Francis, 2023/07/10
- [PULL 23/54] hw/riscv/virt: Restrict ACLINT to TCG, Alistair Francis, 2023/07/10
- [PULL 22/54] target/riscv: Add RVV registers to log, Alistair Francis, 2023/07/10
- [PULL 26/54] target/riscv: Add support for Zfbfmin extension, Alistair Francis, 2023/07/10
- [PULL 27/54] target/riscv: Add support for Zvfbfmin extension, Alistair Francis, 2023/07/10
- [PULL 25/54] target/riscv: Add properties for BF16 extensions, Alistair Francis, 2023/07/10
- [PULL 24/54] linux-user/riscv: Add syscall riscv_hwprobe, Alistair Francis, 2023/07/10
- [PULL 28/54] target/riscv: Add support for Zvfbfwma extension, Alistair Francis, 2023/07/10
- [PULL 29/54] target/riscv: Expose properties for BF16 extensions, Alistair Francis, 2023/07/10
- [PULL 30/54] target/riscv: Set the correct exception for implict G-stage translation fail,
Alistair Francis <=
- [PULL 31/54] target/riscv: Add disas support for BF16 extensions, Alistair Francis, 2023/07/10
- [PULL 35/54] target/riscv: skip features setup for KVM CPUs, Alistair Francis, 2023/07/10
- [PULL 32/54] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly, Alistair Francis, 2023/07/10
- [PULL 33/54] riscv: Generate devicetree only after machine initialization is complete, Alistair Francis, 2023/07/10
- [PULL 34/54] hw/riscv: virt: Convert fdt_load_addr to uint64_t, Alistair Francis, 2023/07/10
- [PULL 36/54] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set, Alistair Francis, 2023/07/10
- [PULL 37/54] target/riscv/cpu.c: restrict 'mvendorid' value, Alistair Francis, 2023/07/10
- [PULL 38/54] target/riscv/cpu.c: restrict 'mimpid' value, Alistair Francis, 2023/07/10
- [PULL 40/54] target/riscv: use KVM scratch CPUs to init KVM properties, Alistair Francis, 2023/07/10
- [PULL 42/54] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs, Alistair Francis, 2023/07/10