Re: [PULL 0/7] target-arm queue

[Richard Henderson]

On 7/17/23 13:47, Peter Maydell wrote:
> A last small test of bug fixes before rc1.
>
> thanks
> -- PMM
>
> The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637:
>
>    Merge tag 'pull-tpm-2023-07-14-1' ofhttps://github.com/stefanberger/qemu-tpm 
>  into staging (2023-07-15 14:54:04 +0100)
>
> are available in the Git repository at:
>
>    https://git.linaro.org/people/pmaydell/qemu-arm.git  
> tags/pull-target-arm-20230717
>
> for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4:
>
>    hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 
> 11:05:52 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>   * hw/arm/sbsa-ref: set 'slots' property of xhci
>   * linux-user: Remove pointless NULL check in clock_adjtime handling
>   * ptw: Fix S1_ptw_translate() debug path
>   * ptw: Account for FEAT_RME when applying {N}SW, SA bits
>   * accel/tcg: Zero-pad PC in TCG CPU exec trace lines
>   * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/8.1 as 
appropriate.


r~