[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH RESEND v5 13/19] target/loongarch: Add LoongArch32 cpu la132
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH RESEND v5 13/19] target/loongarch: Add LoongArch32 cpu la132 |
Date: |
Tue, 22 Aug 2023 09:19:53 +0200 |
From: Jiajie Chen <c@jia.je>
Add LoongArch32 cpu la132.
Due to lack of public documentation of la132, it is currently a
synthetic LoongArch32 cpu model. Details need to be added in the future.
Signed-off-by: Jiajie Chen <c@jia.je>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-10-gaosong@loongson.cn>
---
target/loongarch/cpu.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 67eb6c3135..d3c3e0d8a1 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -440,6 +440,35 @@ static void loongarch_la464_initfn(Object *obj)
env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
}
+static void loongarch_la132_initfn(Object *obj)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+ CPULoongArchState *env = &cpu->env;
+
+ int i;
+
+ for (i = 0; i < 21; i++) {
+ env->cpucfg[i] = 0x0;
+ }
+
+ cpu->dtb_compatible = "loongarch,Loongson-1C103";
+ env->cpucfg[0] = 0x148042; /* PRID */
+
+ uint32_t data = 0;
+ data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
+ data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
+ data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
+ data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
+ data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
+ data = FIELD_DP32(data, CPUCFG1, UAL, 1);
+ data = FIELD_DP32(data, CPUCFG1, RI, 0);
+ data = FIELD_DP32(data, CPUCFG1, EP, 0);
+ data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
+ data = FIELD_DP32(data, CPUCFG1, HP, 1);
+ data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
+ env->cpucfg[1] = data;
+}
+
static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
{
const char *typename = object_class_get_name(OBJECT_CLASS(data));
@@ -787,6 +816,7 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
.class_init = loongarch64_cpu_class_init,
},
DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
+ DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
};
DEFINE_TYPES(loongarch_cpu_type_infos)
--
2.41.0
- [PATCH RESEND v5 03/19] target/loongarch: Support LoongArch32 VPPN, (continued)
- [PATCH RESEND v5 03/19] target/loongarch: Support LoongArch32 VPPN, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 05/19] target/loongarch: Extract make_address_x() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 06/19] target/loongarch: Extract make_address_i() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 07/19] target/loongarch: Extract make_address_pc() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 08/19] target/loongarch: Extract set_pc() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 10/19] target/loongarch: Sign extend results in VA32 mode, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 11/19] target/loongarch: Add a check parameter to the TRANS macro, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 12/19] target/loongarch: Add avail_64 to check la64-only instructions, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 13/19] target/loongarch: Add LoongArch32 cpu la132,
Philippe Mathieu-Daudé <=
- [PATCH RESEND v5 14/19] hw/loongarch: Remove restriction of la464 cores in the virt machine, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 15/19] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 16/19] target/loongarch: Add avail_LSPW to check LSPW instructions, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 17/19] target/loongarch: Add avail_LAM to check atomic instructions, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 19/19] target/loongarch: Add avail_IOCSR to check iocsr instructions, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH RESEND v5 18/19] target/loongarch: Add avail_LSX to check LSX instructions, Philippe Mathieu-Daudé, 2023/08/22
- Re: [PATCH RESEND v5 00/19] Add some checks before translating instructions, gaosong, 2023/08/22