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[PULL 44/48] tcg/tcg-op: Document hswap_i32/64() byte pattern
From: |
Richard Henderson |
Subject: |
[PULL 44/48] tcg/tcg-op: Document hswap_i32/64() byte pattern |
Date: |
Wed, 23 Aug 2023 13:23:22 -0700 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Document hswap_i32() and hswap_i64(), added in commit
46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}").
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230823145542.79633-7-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 22c682c28e..58572526b7 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1108,6 +1108,11 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
}
}
+/*
+ * hswap_i32: Swap 16-bit halfwords within a 32-bit value.
+ *
+ * Byte pattern: abcd -> cdab
+ */
void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg)
{
/* Swapping 2 16-bit elements is a rotate. */
@@ -1921,19 +1926,25 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
}
}
+/*
+ * hswap_i64: Swap 16-bit halfwords within a 64-bit value.
+ * See also include/qemu/bitops.h, hswap64.
+ *
+ * Byte pattern: abcdefgh -> ghefcdab
+ */
void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg)
{
uint64_t m = 0x0000ffff0000ffffull;
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 t1 = tcg_temp_ebb_new_i64();
- /* See include/qemu/bitops.h, hswap64. */
- tcg_gen_rotli_i64(t1, arg, 32);
- tcg_gen_andi_i64(t0, t1, m);
- tcg_gen_shli_i64(t0, t0, 16);
- tcg_gen_shri_i64(t1, t1, 16);
- tcg_gen_andi_i64(t1, t1, m);
- tcg_gen_or_i64(ret, t0, t1);
+ /* arg = abcdefgh */
+ tcg_gen_rotli_i64(t1, arg, 32); /* t1 = efghabcd */
+ tcg_gen_andi_i64(t0, t1, m); /* t0 = ..gh..cd */
+ tcg_gen_shli_i64(t0, t0, 16); /* t0 = gh..cd.. */
+ tcg_gen_shri_i64(t1, t1, 16); /* t1 = ..efghab */
+ tcg_gen_andi_i64(t1, t1, m); /* t1 = ..ef..ab */
+ tcg_gen_or_i64(ret, t0, t1); /* ret = ghefcdab */
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
--
2.34.1
- [PULL 07/48] include/exec: Widen tlb_hit/tlb_hit_page(), (continued)
- [PULL 07/48] include/exec: Widen tlb_hit/tlb_hit_page(), Richard Henderson, 2023/08/23
- [PULL 09/48] accel/tcg: Update run_on_cpu_data static assert, Richard Henderson, 2023/08/23
- [PULL 15/48] tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32, Richard Henderson, 2023/08/23
- [PULL 23/48] target/sparc: Use tcg_gen_movcond_i64 in gen_edge, Richard Henderson, 2023/08/23
- [PULL 26/48] tcg/ppc: Use the Set Boolean Extension, Richard Henderson, 2023/08/23
- [PULL 28/48] tcg/arm: Implement negsetcond_i32, Richard Henderson, 2023/08/23
- [PULL 22/48] target/ppc: Use tcg_gen_negsetcond_*, Richard Henderson, 2023/08/23
- [PULL 38/48] tcg/i386: Implement negsetcond_*, Richard Henderson, 2023/08/23
- [PULL 40/48] tcg/tcg-op: Document bswap16_i64() byte pattern, Richard Henderson, 2023/08/23
- [PULL 41/48] tcg/tcg-op: Document bswap32_i32() byte pattern, Richard Henderson, 2023/08/23
- [PULL 44/48] tcg/tcg-op: Document hswap_i32/64() byte pattern,
Richard Henderson <=
- [PULL 45/48] tcg/tcg-op: Document wswap_i64() byte pattern, Richard Henderson, 2023/08/23
- [PULL 42/48] tcg/tcg-op: Document bswap32_i64() byte pattern, Richard Henderson, 2023/08/23
- [PULL 43/48] tcg/tcg-op: Document bswap64_i64() byte pattern, Richard Henderson, 2023/08/23
- [PULL 47/48] docs/devel/tcg-ops: fix missing newlines in "Host vector operations", Richard Henderson, 2023/08/23
- [PULL 48/48] tcg: spelling fixes, Richard Henderson, 2023/08/23
- [PULL 46/48] target/cris: Fix a typo in gen_swapr(), Richard Henderson, 2023/08/23
- Re: [PULL 00/48] tcg patch queue, Stefan Hajnoczi, 2023/08/24