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[PATCH v2 11/14] tcg/loongarch64: Lower bitsel_vec to vbitsel
From: |
Jiajie Chen |
Subject: |
[PATCH v2 11/14] tcg/loongarch64: Lower bitsel_vec to vbitsel |
Date: |
Fri, 1 Sep 2023 17:31:04 +0800 |
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 11 ++++++++++-
tcg/loongarch64/tcg-target.h | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64/tcg-target-con-set.h
index 13a7f3b5e2..fd2bd785e5 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -35,4 +35,5 @@ C_O1_I2(r, rZ, rZ)
C_O1_I2(w, w, w)
C_O1_I2(w, w, wi)
C_O1_I2(w, w, wJ)
+C_O1_I3(w, w, w, w)
C_O1_I4(r, rZ, rJ, rZ, rZ)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 9f02805c4b..8de4c36396 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1622,7 +1622,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
const int const_args[TCG_MAX_OP_ARGS])
{
TCGType type = vecl + TCG_TYPE_V64;
- TCGArg a0, a1, a2;
+ TCGArg a0, a1, a2, a3;
TCGReg temp = TCG_REG_TMP0;
TCGReg temp_vec = TCG_VEC_TMP0;
@@ -1696,6 +1696,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
a0 = args[0];
a1 = args[1];
a2 = args[2];
+ a3 = args[3];
/* Currently only supports V128 */
tcg_debug_assert(type == TCG_TYPE_V128);
@@ -1863,6 +1864,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sarv_vec:
tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2));
break;
+ case INDEX_op_bitsel_vec:
+ /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
+ tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
+ break;
case INDEX_op_dupm_vec:
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
@@ -1901,6 +1906,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_bitsel_vec:
return 1;
default:
return 0;
@@ -2093,6 +2099,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_neg_vec:
return C_O1_I1(w, w);
+ case INDEX_op_bitsel_vec:
+ return C_O1_I3(w, w, w, w);
+
default:
g_assert_not_reached();
}
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index d27f3737ad..c77672d92c 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -192,7 +192,7 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
--
2.42.0
- Re: [PATCH v2 02/14] tcg/loongarch64: Lower basic tcg vec ops to LSX, (continued)
- [PATCH v2 05/14] tcg/loongarch64: Lower vector bitwise operations, Jiajie Chen, 2023/09/01
- [PATCH v2 06/14] tcg/loongarch64: Lower neg_vec to vneg, Jiajie Chen, 2023/09/01
- [PATCH v2 07/14] tcg/loongarch64: Lower mul_vec to vmul, Jiajie Chen, 2023/09/01
- [PATCH v2 08/14] tcg/loongarch64: Lower vector min max ops, Jiajie Chen, 2023/09/01
- [PATCH v2 09/14] tcg/loongarch64: Lower vector saturated ops, Jiajie Chen, 2023/09/01
- [PATCH v2 10/14] tcg/loongarch64: Lower vector shift vector ops, Jiajie Chen, 2023/09/01
- [PATCH v2 01/14] tcg/loongarch64: Import LSX instructions, Jiajie Chen, 2023/09/01
- [PATCH v2 11/14] tcg/loongarch64: Lower bitsel_vec to vbitsel,
Jiajie Chen <=
- [PATCH v2 13/14] tcg/loongarch64: Lower rotv_vec ops to LSX, Jiajie Chen, 2023/09/01
- [PATCH v2 12/14] tcg/loongarch64: Lower vector shift integer ops, Jiajie Chen, 2023/09/01
- [PATCH v2 14/14] tcg/loongarch64: Lower rotli_vec to vrotri, Jiajie Chen, 2023/09/01