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[PULL v3 10/16] target/tricore: Replace cpu_*_code with translator_*
From: |
Bastian Koppelmann |
Subject: |
[PULL v3 10/16] target/tricore: Replace cpu_*_code with translator_* |
Date: |
Fri, 29 Sep 2023 08:39:54 +0200 |
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-11-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7aba7b067c..2107d1fdd4 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8398,7 +8398,7 @@ static bool insn_crosses_page(CPUTriCoreState *env,
DisasContext *ctx)
* 4 bytes from the page boundary, so we cross the page if the first
* 16 bits indicate that this is a 32 bit insn.
*/
- uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
+ uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next);
return !tricore_insn_is_16bit(insn);
}
@@ -8411,14 +8411,15 @@ static void tricore_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
uint16_t insn_lo;
bool is_16bit;
- insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next);
is_16bit = tricore_insn_is_16bit(insn_lo);
if (is_16bit) {
ctx->opcode = insn_lo;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
decode_16Bit_opc(ctx);
} else {
- uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
+ uint32_t insn_hi = translator_lduw(env, &ctx->base,
+ ctx->base.pc_next + 2);
ctx->opcode = insn_hi << 16 | insn_lo;
ctx->pc_succ_insn = ctx->base.pc_next + 4;
decode_32Bit_opc(ctx);
--
2.42.0
- [PULL v3 00/16] tricore queue, Bastian Koppelmann, 2023/09/29
- [PULL v3 05/16] target/tricore: Clarify special case for FTOUZ insn, Bastian Koppelmann, 2023/09/29
- [PULL v3 04/16] target/tricore: Implement FTOU insn, Bastian Koppelmann, 2023/09/29
- [PULL v3 01/16] tests/tcg/tricore: Bump cpu to tc37x, Bastian Koppelmann, 2023/09/29
- [PULL v3 02/16] target/tricore: Implement CRCN insn, Bastian Koppelmann, 2023/09/29
- [PULL v3 03/16] target/tricore: Correctly handle FPU RM from PSW, Bastian Koppelmann, 2023/09/29
- [PULL v3 08/16] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0, Bastian Koppelmann, 2023/09/29
- [PULL v3 07/16] target/tricore: Implement hptof insn, Bastian Koppelmann, 2023/09/29
- [PULL v3 10/16] target/tricore: Replace cpu_*_code with translator_*,
Bastian Koppelmann <=
- [PULL v3 14/16] tests/tcg: Reset result register after each test, Bastian Koppelmann, 2023/09/29
- [PULL v3 15/16] target/tricore: Remove CSFRs from cpu.h, Bastian Koppelmann, 2023/09/29
- [PULL v3 06/16] target/tricore: Implement ftohp insn, Bastian Koppelmann, 2023/09/29
- [PULL v3 16/16] target/tricore: Change effective address (ea) to target_ulong, Bastian Koppelmann, 2023/09/29
- [PULL v3 09/16] target/tricore: Swap src and dst reg for RCRR_INSERT, Bastian Koppelmann, 2023/09/29
- [PULL v3 11/16] target/tricore: Fix FTOUZ being ISA v1.3.1 up, Bastian Koppelmann, 2023/09/29
- [PULL v3 12/16] tests/tcg/tricore: Extended and non-extened regs now match, Bastian Koppelmann, 2023/09/29
- [PULL v3 13/16] hw/tricore: Log failing test in testdevice, Bastian Koppelmann, 2023/09/29