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Re: [PATCH 2/4] target/riscv: rename ext_icsr to ext_zicsr
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From: |
Alistair Francis |
|
Subject: |
Re: [PATCH 2/4] target/riscv: rename ext_icsr to ext_zicsr |
|
Date: |
Mon, 16 Oct 2023 14:35:40 +1000 |
On Fri, Oct 13, 2023 at 4:27 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add a leading 'z' to improve grepping. When one wants to search for uses
> of zicsr they're more likely to do 'grep -i zicsr' than 'grep -i icsr'.
>
> Suggested-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/boot.c | 2 +-
> target/riscv/cpu.c | 22 +++++++++++-----------
> target/riscv/cpu_cfg.h | 2 +-
> target/riscv/csr.c | 2 +-
> target/riscv/gdbstub.c | 2 +-
> target/riscv/tcg/tcg-cpu.c | 14 +++++++-------
> 6 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 52bf8e67de..0ffca05189 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -414,7 +414,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine,
> RISCVHartArrayState *harts
> reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
> }
>
> - if (!harts->harts[0].cfg.ext_icsr) {
> + if (!harts->harts[0].cfg.ext_zicsr) {
> /*
> * The Zicsr extension has been disabled, so let's ensure we don't
> * run the CSR instruction. Let's fill the address with a non
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index caf42ce68d..fdbbafe7b3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -79,7 +79,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
> ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
> ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
> - ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
> + ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
> ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
> ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
> ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
> @@ -383,7 +383,7 @@ static void riscv_any_cpu_init(Object *obj)
>
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_icsr = true;
> + cpu->cfg.ext_zicsr = true;
> cpu->cfg.mmu = true;
> cpu->cfg.pmp = true;
> }
> @@ -431,7 +431,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_icsr = true;
> + cpu->cfg.ext_zicsr = true;
> cpu->cfg.mmu = true;
> cpu->cfg.pmp = true;
> }
> @@ -449,7 +449,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_icsr = true;
> + cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> }
>
> @@ -495,7 +495,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
> /* Enable ISA extensions */
> cpu->cfg.mmu = true;
> cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_icsr = true;
> + cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> cpu->cfg.ext_icbom = true;
> cpu->cfg.cbom_blocksize = 64;
> @@ -567,7 +567,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_icsr = true;
> + cpu->cfg.ext_zicsr = true;
> cpu->cfg.mmu = true;
> cpu->cfg.pmp = true;
> }
> @@ -585,7 +585,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_icsr = true;
> + cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> }
>
> @@ -603,7 +603,7 @@ static void rv32_ibex_cpu_init(Object *obj)
>
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_icsr = true;
> + cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> }
>
> @@ -620,7 +620,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>
> /* inherited from parent obj via riscv_cpu_init() */
> cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_icsr = true;
> + cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> }
> #endif
> @@ -1243,7 +1243,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> /* Defaults for standard extensions */
> MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
> MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
> - MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
> + MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
> MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
> MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
> MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
> @@ -1348,7 +1348,7 @@ const RISCVCPUMultiExtConfig
> riscv_cpu_experimental_exts[] = {
> /* Deprecated entries marked for future removal */
> const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
> MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
> - MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
> + MULTI_EXT_CFG_BOOL("Zicsr", ext_zicsr, true),
> MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
> MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
> MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index a3f96eb878..9ea30da7e0 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -62,7 +62,7 @@ struct RISCVCPUConfig {
> bool ext_zksh;
> bool ext_zkt;
> bool ext_zifencei;
> - bool ext_icsr;
> + bool ext_zicsr;
> bool ext_icbom;
> bool ext_icboz;
> bool ext_zicond;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4b4ab56c40..30cc21e979 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3858,7 +3858,7 @@ static inline RISCVException
> riscv_csrrw_check(CPURISCVState *env,
> int csr_min_priv = csr_ops[csrno].min_priv_ver;
>
> /* ensure the CSR extension is enabled */
> - if (!riscv_cpu_cfg(env)->ext_icsr) {
> + if (!riscv_cpu_cfg(env)->ext_zicsr) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 524bede865..58b3ace0fe 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -342,7 +342,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState
> *cs)
> g_assert_not_reached();
> }
>
> - if (cpu->cfg.ext_icsr) {
> + if (cpu->cfg.ext_zicsr) {
> int base_reg = cs->gdb_num_regs;
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> riscv_gen_dynamic_csr_xml(cs, base_reg),
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 9b8f3f54a7..418b040d6d 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -278,10 +278,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
> riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
> riscv_has_ext(env, RVD) &&
> - cpu->cfg.ext_icsr && cpu->cfg.ext_zifencei)) {
> + cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) {
>
> - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
> - !cpu->cfg.ext_icsr) {
> + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) &&
> + !cpu->cfg.ext_zicsr) {
> error_setg(errp, "RVG requires Zicsr but user set Zicsr to
> false");
> return;
> }
> @@ -293,7 +293,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> return;
> }
>
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zicsr), true);
> cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true);
>
> env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
> @@ -329,7 +329,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> return;
> }
>
> - if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
> + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) {
> error_setg(errp, "F extension requires Zicsr");
> return;
> }
> @@ -434,7 +434,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> }
>
> if (cpu->cfg.ext_zfinx) {
> - if (!cpu->cfg.ext_icsr) {
> + if (!cpu->cfg.ext_zicsr) {
> error_setg(errp, "Zfinx extension requires Zicsr");
> return;
> }
> @@ -494,7 +494,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> return;
> }
>
> - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
> + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) {
> error_setg(errp, "Zcmt extension requires Zicsr extension");
> return;
> }
> --
> 2.41.0
>
>
- [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*, Daniel Henrique Barboza, 2023/10/12
- [PATCH 1/4] target/riscv: rename ext_ifencei to ext_zifencei, Daniel Henrique Barboza, 2023/10/12
- [PATCH 2/4] target/riscv: rename ext_icsr to ext_zicsr, Daniel Henrique Barboza, 2023/10/12
- Re: [PATCH 2/4] target/riscv: rename ext_icsr to ext_zicsr,
Alistair Francis <=
- [PATCH 3/4] target/riscv: rename ext_icbom to ext_zicbom, Daniel Henrique Barboza, 2023/10/12
- [PATCH 4/4] target/riscv: rename ext_icboz to ext_zicboz, Daniel Henrique Barboza, 2023/10/12
- Re: [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*, Andrew Jones, 2023/10/13
- Re: [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*, Alistair Francis, 2023/10/16