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[PATCH 09/11] hw/net: GMAC Rx Implementation
|
From: |
Nabih Estefan |
|
Subject: |
[PATCH 09/11] hw/net: GMAC Rx Implementation |
|
Date: |
Wed, 18 Oct 2023 18:11:50 +0000 |
From: Nabih Estefan Diaz <nabihestefan@google.com>
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
NOTE: At this point in development we believe this function is working
as intended, and the kernel supports these findings, but we need the
Transmit function to work before we upload
hw/net: npcm_gmac Flush queued packets when starting RX
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP NIC device.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
hw/net: Handle RX desc full in NPCM GMAC
When RX descriptor list is full, it returns a DMA_STATUS for software to handle
it. But there's no way to indicate the software ha handled all RX descriptors
and the whole pipeline stalls.
We do something similar to NPCM7XX EMC to handle this case.
1. Return packet size when RX descriptor is full, effectively dropping these
packets in such a case.
2. When software clears RX descriptor full bit, continue receiving further
packets by flushing QEMU packet queue.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
---
hw/net/npcm_gmac.c | 331 ++++++++++++++++++++++++++++++++++++-
include/hw/net/npcm_gmac.h | 28 ++--
2 files changed, 343 insertions(+), 16 deletions(-)
diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c
index 220955346c..cd59ca5fd4 100644
--- a/hw/net/npcm_gmac.c
+++ b/hw/net/npcm_gmac.c
@@ -23,7 +23,11 @@
#include "hw/registerfields.h"
#include "hw/net/mii.h"
#include "hw/net/npcm_gmac.h"
+#include "linux/if_ether.h"
#include "migration/vmstate.h"
+#include "net/checksum.h"
+#include "net/net.h"
+#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qemu/units.h"
#include "sysemu/dma.h"
@@ -146,6 +150,17 @@ static void gmac_phy_set_link(NPCMGMACState *s, bool
active)
static bool gmac_can_receive(NetClientState *nc)
{
+ NPCMGMACState *gmac = NPCM_GMAC(qemu_get_nic_opaque(nc));
+
+ /* If GMAC receive is disabled. */
+ if (!(gmac->regs[R_NPCM_GMAC_MAC_CONFIG] & NPCM_GMAC_MAC_CONFIG_RX_EN)) {
+ return false;
+ }
+
+ /* If GMAC DMA RX is stopped. */
+ if (!(gmac->regs[R_NPCM_DMA_CONTROL] & NPCM_DMA_CONTROL_START_STOP_RX)) {
+ return false;
+ }
return true;
}
@@ -191,11 +206,288 @@ static void gmac_update_irq(NPCMGMACState *gmac)
qemu_set_irq(gmac->irq, level);
}
-static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t len)
+static int gmac_read_rx_desc(dma_addr_t addr, struct NPCMGMACRxDesc *desc)
+{
+ if (dma_memory_read(&address_space_memory, addr, desc,
+ sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return -1;
+ }
+ desc->rdes0 = le32_to_cpu(desc->rdes0);
+ desc->rdes1 = le32_to_cpu(desc->rdes1);
+ desc->rdes2 = le32_to_cpu(desc->rdes2);
+ desc->rdes3 = le32_to_cpu(desc->rdes3);
+ return 0;
+}
+
+static int gmac_write_rx_desc(dma_addr_t addr, struct NPCMGMACRxDesc *desc)
+{
+ struct NPCMGMACRxDesc le_desc;
+ le_desc.rdes0 = cpu_to_le32(desc->rdes0);
+ le_desc.rdes1 = cpu_to_le32(desc->rdes1);
+ le_desc.rdes2 = cpu_to_le32(desc->rdes2);
+ le_desc.rdes3 = cpu_to_le32(desc->rdes3);
+ if (dma_memory_write(&address_space_memory, addr, &le_desc,
+ sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return -1;
+ }
+ return 0;
+}
+
+static int gmac_read_tx_desc(dma_addr_t addr, struct NPCMGMACTxDesc *desc)
+{
+ if (dma_memory_read(&address_space_memory, addr, desc,
+ sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return -1;
+ }
+ desc->tdes0 = le32_to_cpu(desc->tdes0);
+ desc->tdes1 = le32_to_cpu(desc->tdes1);
+ desc->tdes2 = le32_to_cpu(desc->tdes2);
+ desc->tdes3 = le32_to_cpu(desc->tdes3);
+ return 0;
+}
+
+static int gmac_write_tx_desc(dma_addr_t addr, struct NPCMGMACTxDesc *desc)
{
- /* Placeholder */
+ struct NPCMGMACTxDesc le_desc;
+ le_desc.tdes0 = cpu_to_le32(desc->tdes0);
+ le_desc.tdes1 = cpu_to_le32(desc->tdes1);
+ le_desc.tdes2 = cpu_to_le32(desc->tdes2);
+ le_desc.tdes3 = cpu_to_le32(desc->tdes3);
+ if (dma_memory_write(&address_space_memory, addr, &le_desc,
+ sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0x%"
+ HWADDR_PRIx "\n", __func__, addr);
+ return -1;
+ }
return 0;
}
+static int gmac_rx_transfer_frame_to_buffer(uint32_t rx_buf_len,
+ uint32_t *left_frame,
+ uint32_t rx_buf_addr,
+ bool *eof_transferred,
+ const uint8_t **frame_ptr,
+ uint16_t *transferred)
+{
+ uint32_t to_transfer;
+ /*
+ * Check that buffer is bigger than the frame being transfered
+ * If bigger then transfer only whats left of frame
+ * Else, fill frame with all the content possible
+ */
+ if (rx_buf_len >= *left_frame) {
+ to_transfer = *left_frame;
+ *eof_transferred = true;
+ } else {
+ to_transfer = rx_buf_len;
+ }
+
+ /* write frame part to memory */
+ if (dma_memory_write(&address_space_memory, (uint64_t) rx_buf_addr,
+ *frame_ptr, to_transfer, MEMTXATTRS_UNSPECIFIED))
+ {
+ return -1;
+ }
+
+ /* update frame pointer and size of whats left of frame */
+ *frame_ptr += to_transfer;
+ *left_frame -= to_transfer;
+ *transferred += to_transfer;
+
+ return 0;
+}
+
+static void gmac_dma_set_state(NPCMGMACState *gmac, int shift, uint32_t state)
+{
+ gmac->regs[R_NPCM_DMA_STATUS] = deposit32(gmac->regs[R_NPCM_DMA_STATUS],
+ shift, 3, state);
+}
+
+static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t len)
+{
+ /*
+ * Comments have steps that relate to the
+ * receiving process steps in pg 386
+ */
+ NPCMGMACState *gmac = NPCM_GMAC(qemu_get_nic_opaque(nc));
+ uint32_t left_frame = len;
+ const uint8_t *frame_ptr = buf;
+ uint32_t desc_addr;
+ uint32_t rx_buf_len, rx_buf_addr;
+ struct NPCMGMACRxDesc rx_desc;
+ uint16_t transferred = 0;
+ bool eof_transferred = false;
+
+ trace_npcm_gmac_packet_receive(DEVICE(gmac)->canonical_path, len);
+ if (!gmac_can_receive(nc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "GMAC Currently is not able for Rx");
+ return -1;
+ }
+ if (!gmac->regs[R_NPCM_DMA_HOST_RX_DESC]) {
+ gmac->regs[R_NPCM_DMA_HOST_RX_DESC] =
+ NPCM_DMA_HOST_RX_DESC_MASK(gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]);
+ }
+ desc_addr =
NPCM_DMA_HOST_RX_DESC_MASK(gmac->regs[R_NPCM_DMA_HOST_RX_DESC]);
+
+ /* step 1 */
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_RUNNING_FETCHING_STATE);
+ trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path, desc_addr);
+ if (gmac_read_rx_desc(desc_addr, &rx_desc)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "RX Descriptor @ 0x%x cant be read\n",
+ desc_addr);
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_SUSPENDED_STATE);
+ return -1;
+ }
+
+ /* step 2 */
+ if (!(rx_desc.rdes0 & RX_DESC_RDES0_OWN)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "RX Descriptor @ 0x%x is owned by software\n",
+ desc_addr);
+ gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_RU;
+ gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_RI;
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_SUSPENDED_STATE);
+ gmac_update_irq(gmac);
+ return len;
+ }
+ /* step 3 */
+ /*
+ * TODO --
+ * Implement all frame filtering and processing (with its own interrupts)
+ */
+ trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_desc,
+ rx_desc.rdes0, rx_desc.rdes1,
rx_desc.rdes2,
+ rx_desc.rdes3);
+ /* Clear rdes0 for the incoming descriptor and set FS in first
descriptor.*/
+ rx_desc.rdes0 = RX_DESC_RDES0_FIRST_DESC_MASK;
+
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_RUNNING_TRANSFERRING_STATE);
+
+ /* Pad the frame with FCS as the kernel driver will strip it away. */
+ left_frame += ETH_FCS_LEN;
+
+ /* repeat while we still have frame to transfer to memory */
+ while (!eof_transferred) {
+ /* Return descriptor no matter what happens */
+ rx_desc.rdes0 &= ~RX_DESC_RDES0_OWN;
+ /* Set the frame to be an IPv4/IPv6 frame. */
+ rx_desc.rdes0 |= RX_DESC_RDES0_FRM_TYPE_MASK;
+
+ /* step 4 */
+ rx_buf_len = RX_DESC_RDES1_BFFR1_SZ_MASK(rx_desc.rdes1);
+ rx_buf_addr = rx_desc.rdes2;
+ gmac->regs[R_NPCM_DMA_CUR_RX_BUF_ADDR] = rx_buf_addr;
+ gmac_rx_transfer_frame_to_buffer(rx_buf_len, &left_frame, rx_buf_addr,
+ &eof_transferred, &frame_ptr,
+ &transferred);
+
+ trace_npcm_gmac_packet_receiving_buffer(DEVICE(gmac)->canonical_path,
+ rx_buf_len, rx_buf_addr);
+ /* if we still have frame left and the second buffer is not chained */
+ if (!(rx_desc.rdes1 & RX_DESC_RDES1_SEC_ADDR_CHND_MASK) && \
+ !eof_transferred) {
+ /* repeat process from above on buffer 2 */
+ rx_buf_len = RX_DESC_RDES1_BFFR2_SZ_MASK(rx_desc.rdes1);
+ rx_buf_addr = rx_desc.rdes3;
+ gmac->regs[R_NPCM_DMA_CUR_RX_BUF_ADDR] = rx_buf_addr;
+ gmac_rx_transfer_frame_to_buffer(rx_buf_len, &left_frame,
+ rx_buf_addr, &eof_transferred,
+ &frame_ptr, &transferred);
+ trace_npcm_gmac_packet_receiving_buffer( \
+ DEVICE(gmac)->canonical_path,
+ rx_buf_len, rx_buf_addr);
+ }
+ /* update address for descriptor */
+ gmac->regs[R_NPCM_DMA_HOST_RX_DESC] = rx_buf_addr;
+ /* Return descriptor */
+ rx_desc.rdes0 &= ~RX_DESC_RDES0_OWN;
+ /* Update frame length transferred */
+ rx_desc.rdes0 |= ((uint32_t)transferred)
+ << RX_DESC_RDES0_FRAME_LEN_SHIFT;
+ trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_desc,
+ rx_desc.rdes0, rx_desc.rdes1,
+ rx_desc.rdes2, rx_desc.rdes3);
+
+ /* step 5 */
+ gmac_write_rx_desc(desc_addr, &rx_desc);
+ trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path,
+ &rx_desc, rx_desc.rdes0,
+ rx_desc.rdes1, rx_desc.rdes2,
+ rx_desc.rdes3);
+ /* read new descriptor into rx_desc if needed*/
+ if (!eof_transferred) {
+ /* Get next descriptor address (chained or sequential) */
+ if (rx_desc.rdes1 & RX_DESC_RDES1_RC_END_RING_MASK) {
+ desc_addr = gmac->regs[R_NPCM_DMA_RX_BASE_ADDR];
+ } else if (rx_desc.rdes1 & RX_DESC_RDES1_SEC_ADDR_CHND_MASK) {
+ desc_addr = rx_desc.rdes3;
+ } else {
+ desc_addr += sizeof(rx_desc);
+ }
+ trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path,
+ desc_addr);
+ if (gmac_read_rx_desc(desc_addr, &rx_desc)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "RX Descriptor @ 0x%x cant be read\n",
+ desc_addr);
+ gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_RU;
+ gmac_update_irq(gmac);
+ return len;
+ }
+
+ /* step 6 */
+ if (!(rx_desc.rdes0 & RX_DESC_RDES0_OWN)) {
+ if (!(gmac->regs[R_NPCM_DMA_CONTROL] & \
+ NPCM_DMA_CONTROL_FLUSH_MASK)) {
+ rx_desc.rdes0 |= RX_DESC_RDES0_DESC_ERR_MASK;
+ }
+ eof_transferred = true;
+ }
+ /* Clear rdes0 for the incoming descriptor */
+ rx_desc.rdes0 = 0;
+ }
+ }
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_RUNNING_CLOSING_STATE);
+
+ rx_desc.rdes0 |= RX_DESC_RDES0_LAST_DESC_MASK;
+ if (!(rx_desc.rdes1 & RX_DESC_RDES1_DIS_INTR_COMP_MASK)) {
+ gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_RI;
+ gmac_update_irq(gmac);
+ }
+ trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_desc,
+ rx_desc.rdes0, rx_desc.rdes1,
rx_desc.rdes2,
+ rx_desc.rdes3);
+
+ /* step 8 */
+ gmac->regs[R_NPCM_DMA_CONTROL] |= NPCM_DMA_CONTROL_FLUSH_MASK;
+
+ /* step 9 */
+ trace_npcm_gmac_packet_received(DEVICE(gmac)->canonical_path, left_frame);
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE);
+ gmac_write_rx_desc(desc_addr, &rx_desc);
+
+ /* Get next descriptor address (chained or sequential) */
+ if (rx_desc.rdes1 & RX_DESC_RDES1_RC_END_RING_MASK) {
+ desc_addr = gmac->regs[R_NPCM_DMA_RX_BASE_ADDR];
+ } else if (rx_desc.rdes1 & RX_DESC_RDES1_SEC_ADDR_CHND_MASK) {
+ desc_addr = rx_desc.rdes3;
+ } else {
+ desc_addr += sizeof(rx_desc);
+ }
+ gmac->regs[R_NPCM_DMA_HOST_RX_DESC] = desc_addr;
+ return len;
+}
static void gmac_cleanup(NetClientState *nc)
{
/* Nothing to do yet. */
@@ -281,7 +573,6 @@ static void npcm_gmac_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size)
{
NPCMGMACState *gmac = opaque;
- uint32_t prev;
trace_npcm_gmac_reg_write(DEVICE(gmac)->canonical_path, offset, v);
@@ -305,6 +596,7 @@ static void npcm_gmac_write(void *opaque, hwaddr offset,
break;
case A_NPCM_GMAC_MAC_CONFIG:
+ gmac->regs[offset / sizeof(uint32_t)] = v;
break;
case A_NPCM_GMAC_MII_ADDR:
@@ -346,6 +638,31 @@ static void npcm_gmac_write(void *opaque, hwaddr offset,
case A_NPCM_DMA_RCV_POLL_DEMAND:
/* We dont actually care about the value */
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE);
+ break;
+
+ case A_NPCM_DMA_XMT_POLL_DEMAND:
+ /* We dont actually care about the value */
+ gmac_try_send_next_packet(gmac);
+ break;
+
+ case A_NPCM_DMA_CONTROL:
+ gmac->regs[offset / sizeof(uint32_t)] = v;
+ if (v & NPCM_DMA_CONTROL_START_STOP_TX) {
+ gmac_try_send_next_packet(gmac);
+ } else {
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_TX_STOPPED_STATE);
+ }
+ if (v & NPCM_DMA_CONTROL_START_STOP_RX) {
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE);
+ qemu_flush_queued_packets(qemu_get_queue(gmac->nic));
+ } else {
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_STOPPED_STATE);
+ }
break;
case A_NPCM_DMA_STATUS:
@@ -356,6 +673,14 @@ static void npcm_gmac_write(void *opaque, hwaddr offset,
HWADDR_PRIx ", value: 0x%04" PRIx64 "\n",
DEVICE(gmac)->canonical_path, offset, v);
}
+ /* for W1C bits, implement W1C */
+ gmac->regs[offset / sizeof(uint32_t)] &= ~NPCM_DMA_STATUS_W1C_MASK(v);
+ if (v & NPCM_DMA_STATUS_RU) {
+ /* Clearing RU bit indicates descriptor is owned by DMA again. */
+ gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT,
+ NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE);
+ qemu_flush_queued_packets(qemu_get_queue(gmac->nic));
+ }
break;
default:
diff --git a/include/hw/net/npcm_gmac.h b/include/hw/net/npcm_gmac.h
index c97eb6fe6e..d0a37e6988 100644
--- a/include/hw/net/npcm_gmac.h
+++ b/include/hw/net/npcm_gmac.h
@@ -136,7 +136,7 @@ struct NPCMGMACTxDesc {
#define TX_DESC_TDES1_INTERR_COMP_MASK BIT(31)
/* Last Segment */
#define TX_DESC_TDES1_LAST_SEG_MASK BIT(30)
-/* Last Segment */
+/* First Segment */
#define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29)
/* Checksum Insertion Control */
#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 2)
@@ -176,32 +176,32 @@ OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC)
#define NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT 20
/* Transmit States */
#define NPCM_DMA_STATUS_TX_STOPPED_STATE \
- (0b000 << NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT)
+ (0b000)
#define NPCM_DMA_STATUS_TX_RUNNING_FETCHING_STATE \
- (0b001 << NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT)
+ (0b001)
#define NPCM_DMA_STATUS_TX_RUNNING_WAITING_STATE \
- (0b010 << NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT)
+ (0b010)
#define NPCM_DMA_STATUS_TX_RUNNING_READ_STATE \
- (0b011 << NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT)
+ (0b011)
#define NPCM_DMA_STATUS_TX_SUSPENDED_STATE \
- (0b110 << NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT)
+ (0b110)
#define NPCM_DMA_STATUS_TX_RUNNING_CLOSING_STATE \
- (0b111 << NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT)
+ (0b111)
/* Transmit Process State */
#define NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT 17
/* Receive States */
#define NPCM_DMA_STATUS_RX_STOPPED_STATE \
- (0b000 << NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT)
+ (0b000)
#define NPCM_DMA_STATUS_RX_RUNNING_FETCHING_STATE \
- (0b001 << NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT)
+ (0b001)
#define NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE \
- (0b011 << NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT)
+ (0b011)
#define NPCM_DMA_STATUS_RX_SUSPENDED_STATE \
- (0b100 << NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT)
+ (0b100)
#define NPCM_DMA_STATUS_RX_RUNNING_CLOSING_STATE \
- (0b101 << NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT)
+ (0b101)
#define NPCM_DMA_STATUS_RX_RUNNING_TRANSFERRING_STATE \
- (0b111 << NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT)
+ (0b111)
/* Early Receive Interrupt */
@@ -302,6 +302,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC)
#define NPCM_DMA_CONTROL_FLUSH_MASK BIT(24)
/* Start/stop Transmit */
#define NPCM_DMA_CONTROL_START_STOP_TX BIT(13)
+/* Start/stop Receive */
+#define NPCM_DMA_CONTROL_START_STOP_RX BIT(1)
/* Next receive descriptor start address */
#define NPCM_DMA_HOST_RX_DESC_MASK(word) ((uint32_t) (word) & ~3u)
/* Next transmit descriptor start address */
--
2.42.0.655.g421f12c284-goog
- [PATCH 11/11] tests/qtest: Adding PCS Module test to GMAC Qtest, (continued)
- [PATCH 11/11] tests/qtest: Adding PCS Module test to GMAC Qtest, Nabih Estefan, 2023/10/17
- [PATCH 00/11] Implementation of NPI Mailbox and GMAC Networking Module, Nabih Estefan, 2023/10/18
- [PATCH 01/11] hw/misc: Add Nuvoton's PCI Mailbox Module, Nabih Estefan, 2023/10/18
- [PATCH 02/11] hw/arm: Add PCI mailbox module to Nuvoton SoC, Nabih Estefan, 2023/10/18
- [PATCH 03/11] hw/misc: Add qtest for NPCM7xx PCI Mailbox, Nabih Estefan, 2023/10/18
- [PATCH 04/11] hw/net: Add NPCMXXX GMAC device, Nabih Estefan, 2023/10/18
- [PATCH 05/11] hw/arm: Add GMAC devices to NPCM7XX SoC, Nabih Estefan, 2023/10/18
- [PATCH 06/11] tests/qtest: Creating qtest for GMAC Module, Nabih Estefan, 2023/10/18
- [PATCH 07/11] include/hw/net: Implemented Classes and Masks for GMAC Descriptors, Nabih Estefan, 2023/10/18
- [PATCH 08/11] hw/net: General GMAC Implementation, Nabih Estefan, 2023/10/18
- [PATCH 09/11] hw/net: GMAC Rx Implementation,
Nabih Estefan <=
- [PATCH 10/11] hw/net: GMAC Tx Implementation, Nabih Estefan, 2023/10/18
- [PATCH 11/11] tests/qtest: Adding PCS Module test to GMAC Qtest, Nabih Estefan, 2023/10/18