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[PATCH v2 17/19] target/i386: move remaining conditional operations to n
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From: |
Paolo Bonzini |
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Subject: |
[PATCH v2 17/19] target/i386: move remaining conditional operations to new decoder |
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Date: |
Thu, 19 Oct 2023 12:48:05 +0200 |
Move long-displacement Jcc, SETcc and CMOVcc to the new decoder.
While filling in the tables makes the code seem longer, the new
emitters are all just one line of code.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 56 ++++++++++++++++++++++++++++++++
target/i386/tcg/decode-new.h | 1 +
target/i386/tcg/emit.c.inc | 10 ++++++
target/i386/tcg/translate.c | 4 ++-
4 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index d0baf972208..e68f5ae068e 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -944,6 +944,15 @@ static const X86OpEntry opcodes_0F[256] = {
/* Incorrectly listed as Mq,Vq in the manual */
[0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_66),
+ [0x40] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x41] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x42] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x43] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x44] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x45] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x46] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x47] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+
[0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
[0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3
p_00_66_f3_f2), /* sqrtps */
[0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), /*
rsqrtps */
@@ -971,6 +980,24 @@ static const X86OpEntry opcodes_0F[256] = {
[0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256
p_00_66),
[0x77] = X86_OP_GROUP0(0F77),
+ [0x80] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x81] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x82] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x83] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x84] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x85] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x86] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x87] = X86_OP_ENTRYr(Jcc, J,z),
+
+ [0x90] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x91] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x92] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x93] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x94] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x95] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x96] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x97] = X86_OP_ENTRYw(SETcc, E,b),
+
[0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /*
MOVAPS */
[0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /*
MOVAPS */
[0x2A] = X86_OP_GROUP0(0F2A),
@@ -983,6 +1010,15 @@ static const X86OpEntry opcodes_0F[256] = {
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),
+ [0x48] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x49] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4a] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4b] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4c] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4d] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4e] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+ [0x4f] = X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)),
+
[0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
[0x5a] = X86_OP_GROUP0(0F5A),
@@ -1008,6 +1044,24 @@ static const X86OpEntry opcodes_0F[256] = {
[0x7e] = X86_OP_GROUP0(0F7E),
[0x7f] = X86_OP_GROUP0(0F7F),
+ [0x88] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x89] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x8a] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x8b] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x8c] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x8d] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x8e] = X86_OP_ENTRYr(Jcc, J,z),
+ [0x8f] = X86_OP_ENTRYr(Jcc, J,z),
+
+ [0x98] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x99] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9a] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9b] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9c] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9d] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9e] = X86_OP_ENTRYw(SETcc, E,b),
+ [0x9f] = X86_OP_ENTRYw(SETcc, E,b),
+
[0xae] = X86_OP_GROUP0(group15),
[0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3
p_00_66_f3_f2),
@@ -1743,6 +1797,8 @@ static bool has_cpuid_feature(DisasContext *s,
X86CPUIDFeature cpuid)
switch (cpuid) {
case X86_FEAT_None:
return true;
+ case X86_FEAT_CMOV:
+ return (s->cpuid_features & CPUID_CMOV);
case X86_FEAT_F16C:
return (s->cpuid_ext_features & CPUID_EXT_F16C);
case X86_FEAT_FMA:
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index 32396630865..119de3bf342 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -105,6 +105,7 @@ typedef enum X86CPUIDFeature {
X86_FEAT_AVX2,
X86_FEAT_BMI1,
X86_FEAT_BMI2,
+ X86_FEAT_CMOV,
X86_FEAT_CMPCCXADD,
X86_FEAT_F16C,
X86_FEAT_FMA,
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 267f4fe383a..05e1fb16844 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1636,6 +1636,16 @@ static void gen_Jcc(DisasContext *s, CPUX86State *env,
X86DecodedInsn *decode)
gen_jcc(s, decode->b & 0xf, decode->immediate);
}
+static void gen_SETcc(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
+{
+ gen_setcc1(s, decode->b & 0xf, s->T0);
+}
+
+static void gen_CMOVcc(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
+{
+ gen_cmovcc1(s, decode->b & 0xf, s->T0, s->T1);
+}
+
static void gen_LAHF(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) {
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 2c4e680a69e..1f3cc6361c0 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3186,7 +3186,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
#ifndef CONFIG_USER_ONLY
use_new &= b <= limit;
#endif
- if (use_new && 0) {
+ if (use_new &&
+ ((b >= 0x140 && b <= 0x14f) ||
+ (b >= 0x180 && b <= 0x19f))) {
disas_insn_new(s, cpu, b);
return true;
}
--
2.41.0
- [PATCH v2 08/19] target/i386: implement CMPccXADD, (continued)
- [PATCH v2 08/19] target/i386: implement CMPccXADD, Paolo Bonzini, 2023/10/19
- [PATCH v2 11/19] target/i386: move 00-5F opcodes to new decoder, Paolo Bonzini, 2023/10/19
- [PATCH v2 09/19] target/i386: do not clobber A0 in POP translation, Paolo Bonzini, 2023/10/19
- [PATCH v2 14/19] tcg: add negsetcondi, Paolo Bonzini, 2023/10/19
- [PATCH v2 07/19] target/i386: introduce flags writeback mechanism, Paolo Bonzini, 2023/10/19
- [PATCH v2 10/19] target/i386: reintroduce debugging mechanism, Paolo Bonzini, 2023/10/19
- [PATCH v2 13/19] target/i386: split eflags computation out of gen_compute_eflags, Paolo Bonzini, 2023/10/19
- [PATCH v2 12/19] target/i386: adjust decoding of J operand, Paolo Bonzini, 2023/10/19
- [PATCH v2 16/19] target/i386: move operand load and writeback out of gen_cmovcc1, Paolo Bonzini, 2023/10/19
- [PATCH v2 15/19] target/i386: move 60-BF opcodes to new decoder, Paolo Bonzini, 2023/10/19
- [PATCH v2 17/19] target/i386: move remaining conditional operations to new decoder,
Paolo Bonzini <=
- [PATCH v2 19/19] target/i386: remove gen_op, Paolo Bonzini, 2023/10/19
- [PATCH v2 18/19] target/i386: remove now converted opcodes from old decoder, Paolo Bonzini, 2023/10/19
- Re: [PATCH v2 00/19] target/i386: decoder changes for 8.2, Paolo Bonzini, 2023/10/19
- Re: [PATCH v2 00/19] target/i386: decoder changes for 8.2, Richard Henderson, 2023/10/19