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[PATCH v2 53/65] target/hppa: Implement HSUB
From: |
Richard Henderson |
Subject: |
[PATCH v2 53/65] target/hppa: Implement HSUB |
Date: |
Fri, 20 Oct 2023 13:43:19 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 2 ++
target/hppa/insns.decode | 4 ++++
target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++
target/hppa/translate.c | 15 +++++++++++++++
4 files changed, 53 insertions(+)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index ff2695797e..99486f4cf8 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -16,6 +16,8 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64)
+DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64)
+DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 88248ed3e2..1830b06c76 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -214,6 +214,10 @@ hadd 000010 ..... ..... 00000011 11 0 .....
@rrr
hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr
hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr
+hsub 000010 ..... ..... 00000001 11 0 ..... @rrr
+hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr
+hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr
+
####
# Index Mem
####
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index a230a3a0c3..ece523bea0 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -409,3 +409,35 @@ uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2)
}
return ret;
}
+
+uint64_t HELPER(hsub_ss)(uint64_t r1, uint64_t r2)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = sextract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = f1 - f2;
+
+ fr = MIN(fr, INT16_MAX);
+ fr = MAX(fr, INT16_MIN);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
+
+uint64_t HELPER(hsub_us)(uint64_t r1, uint64_t r2)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = extract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = f1 - f2;
+
+ fr = MIN(fr, UINT16_MAX);
+ fr = MAX(fr, 0);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 0d72c96fd5..63c6a28cef 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2776,6 +2776,21 @@ static bool trans_hadd_us(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_helper_hadd_us);
}
+static bool trans_hsub(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64);
+}
+
+static bool trans_hsub_ss(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_helper_hsub_ss);
+}
+
+static bool trans_hsub_us(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_helper_hsub_us);
+}
+
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
if (!ctx->is_pa20 && a->size > MO_32) {
--
2.34.1
- [PATCH v2 36/65] target/hppa: Decode d for cmpb instructions, (continued)
- [PATCH v2 36/65] target/hppa: Decode d for cmpb instructions, Richard Henderson, 2023/10/20
- [PATCH v2 41/65] target/hppa: Implement EXTRD, Richard Henderson, 2023/10/20
- [PATCH v2 40/65] target/hppa: Implement DEPD, DEPDI, Richard Henderson, 2023/10/20
- [PATCH v2 42/65] target/hppa: Implement SHRPD, Richard Henderson, 2023/10/20
- [PATCH v2 43/65] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM, Richard Henderson, 2023/10/20
- [PATCH v2 44/65] target/hppa: Implement STDBY, Richard Henderson, 2023/10/20
- [PATCH v2 46/65] hw/hppa: Use uint32_t instead of target_ureg, Richard Henderson, 2023/10/20
- [PATCH v2 45/65] target/hppa: Implement IDTLBT, IITLBT, Richard Henderson, 2023/10/20
- [PATCH v2 47/65] target/hppa: Remove TARGET_REGISTER_BITS, Richard Henderson, 2023/10/20
- [PATCH v2 51/65] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64, Richard Henderson, 2023/10/20
- [PATCH v2 53/65] target/hppa: Implement HSUB,
Richard Henderson <=
- [PATCH v2 49/65] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/10/20
- [PATCH v2 48/65] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/10/20
- [PATCH v2 52/65] target/hppa: Implement HADD, Richard Henderson, 2023/10/20
- [PATCH v2 54/65] target/hppa: Implement HAVG, Richard Henderson, 2023/10/20
- [PATCH v2 55/65] target/hppa: Implement HSHL, HSHR, Richard Henderson, 2023/10/20
- [PATCH v2 56/65] target/hppa: Implement HSHLADD, HSHRADD, Richard Henderson, 2023/10/20
- [PATCH v2 50/65] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new, Richard Henderson, 2023/10/20
- [PATCH v2 57/65] target/hppa: Implement MIXH, MIXW, Richard Henderson, 2023/10/20
- [PATCH v2 58/65] target/hppa: Implement PERMH, Richard Henderson, 2023/10/20
- [PATCH v2 60/65] target/hppa: Precompute zero into DisasContext, Richard Henderson, 2023/10/20