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[PATCH v5 11/94] target/sparc: Define AM_CHECK for sparc32
From: |
Richard Henderson |
Subject: |
[PATCH v5 11/94] target/sparc: Define AM_CHECK for sparc32 |
Date: |
Sun, 22 Oct 2023 16:28:09 -0700 |
Define as false, which allows some ifdef removal.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 080bc5f8a2..9eb2b7e52f 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -268,20 +268,21 @@ static void gen_move_Q(DisasContext *dc, unsigned int rd,
unsigned int rs)
#endif
#endif
-#ifdef TARGET_SPARC64
-#ifndef TARGET_ABI32
-#define AM_CHECK(dc) ((dc)->address_mask_32bit)
+#if !defined(TARGET_SPARC64)
+# define AM_CHECK(dc) false
+#elif defined(TARGET_ABI32)
+# define AM_CHECK(dc) true
+#elif defined(CONFIG_USER_ONLY)
+# define AM_CHECK(dc) false
#else
-#define AM_CHECK(dc) (1)
-#endif
+# define AM_CHECK(dc) ((dc)->address_mask_32bit)
#endif
static void gen_address_mask(DisasContext *dc, TCGv addr)
{
-#ifdef TARGET_SPARC64
- if (AM_CHECK(dc))
+ if (AM_CHECK(dc)) {
tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
-#endif
+ }
}
static TCGv gen_load_gpr(DisasContext *dc, int reg)
@@ -1366,11 +1367,9 @@ static void do_branch(DisasContext *dc, int32_t offset,
uint32_t insn, int cc)
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
target_ulong target = dc->pc + offset;
-#ifdef TARGET_SPARC64
if (unlikely(AM_CHECK(dc))) {
target &= 0xffffffffULL;
}
-#endif
if (cond == 0x0) {
/* unconditional not taken */
if (a) {
@@ -1406,11 +1405,9 @@ static void do_fbranch(DisasContext *dc, int32_t offset,
uint32_t insn, int cc)
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
target_ulong target = dc->pc + offset;
-#ifdef TARGET_SPARC64
if (unlikely(AM_CHECK(dc))) {
target &= 0xffffffffULL;
}
-#endif
if (cond == 0x0) {
/* unconditional not taken */
if (a) {
--
2.34.1
- [PATCH v5 00/94] target/sparc: Convert to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 03/94] target/sparc: Avoid helper_raise_exception in helper_st_asi, Richard Henderson, 2023/10/22
- [PATCH v5 02/94] target/sparc: Implement check_align inline, Richard Henderson, 2023/10/22
- [PATCH v5 05/94] configs: Enable MTTCG for sparc, sparc64, Richard Henderson, 2023/10/22
- [PATCH v5 06/94] target/sparc: Define features via cpu-feature.h.inc, Richard Henderson, 2023/10/22
- [PATCH v5 07/94] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties, Richard Henderson, 2023/10/22
- [PATCH v5 04/94] target/sparc: Set TCG_GUEST_DEFAULT_MO, Richard Henderson, 2023/10/22
- [PATCH v5 01/94] target/sparc: Clear may_lookup for npc == DYNAMIC_PC, Richard Henderson, 2023/10/22
- [PATCH v5 08/94] target/sparc: Remove sparcv7 cpu features, Richard Henderson, 2023/10/22
- [PATCH v5 11/94] target/sparc: Define AM_CHECK for sparc32,
Richard Henderson <=
- [PATCH v5 09/94] target/sparc: Partition cpu features, Richard Henderson, 2023/10/22
- [PATCH v5 14/94] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 22/94] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 25/94] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 17/94] target/sparc: Merge gen_fcond with only caller, Richard Henderson, 2023/10/22
- [PATCH v5 12/94] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 15/94] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 18/94] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/22
- [PATCH v5 26/94] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v5 30/94] target/sparc: Remove cpu_wim, Richard Henderson, 2023/10/22